651bdb96b1
This was [addressed for AArch64 here](https://github.com/llvm/llvm-project/pull/79004), but the same applies to ARM. Move the enablement of neon+fp64 to `-mcpu=cortex-r52`, which optionally supports these features.
25 lines
864 B
LLVM
25 lines
864 B
LLVM
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
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; RUN: llc < %s -mtriple=armv7m-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
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; RUN: llc < %s -mtriple=armv8m-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
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; Check we use AA during codegen, so can interleave these loads/stores.
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; CHECK-LABEL: test
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; USEAA: ldr
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; USEAA: ldr
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; USEAA: str
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; USEAA: str
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define void @test(ptr nocapture %a, ptr noalias nocapture %b) {
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entry:
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%0 = load i32, ptr %a, align 4
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%add = add nsw i32 %0, 10
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store i32 %add, ptr %a, align 4
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%1 = load i32, ptr %b, align 4
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%add2 = add nsw i32 %1, 20
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store i32 %add2, ptr %b, align 4
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ret void
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}
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