4d7f3d9e0f
Need to check that at least single bit is cleared for unsigned nodes before reducing their size. Otherwise they might be treated as signed in signed nodes.
80 lines
4.0 KiB
LLVM
80 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux -mattr=+v < %s | FileCheck %s
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define void @test(ptr %p, i16 %load794) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[P:%.*]], i16 [[LOAD794:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ZEXT795:%.*]] = zext i16 [[LOAD794]] to i32
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; CHECK-NEXT: [[GEP799:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 16
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; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[P]], align 2
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i16>, ptr [[GEP799]], align 2
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; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32>
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; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32>
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; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <2 x i32> [[TMP4]], [[TMP3]]
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; CHECK-NEXT: [[TMP8:%.*]] = add nsw <2 x i32> [[TMP7]], <i32 3329, i32 3329>
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; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[ZEXT795]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i32> [[TMP8]], [[TMP6]]
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; CHECK-NEXT: [[TMP9:%.*]] = zext <2 x i32> [[TMP12]] to <2 x i64>
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; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw <2 x i64> [[TMP9]], <i64 5039, i64 5039>
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; CHECK-NEXT: [[TMP11:%.*]] = lshr <2 x i64> [[TMP10]], <i64 24, i64 24>
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; CHECK-NEXT: [[TMP13:%.*]] = trunc <2 x i64> [[TMP11]] to <2 x i32>
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; CHECK-NEXT: [[TMP20:%.*]] = mul <2 x i32> [[TMP13]], <i32 62207, i32 62207>
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; CHECK-NEXT: [[TMP21:%.*]] = add <2 x i32> [[TMP20]], [[TMP12]]
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; CHECK-NEXT: [[TMP14:%.*]] = trunc <2 x i32> [[TMP21]] to <2 x i16>
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; CHECK-NEXT: [[TMP15:%.*]] = add <2 x i16> [[TMP14]], <i16 -3329, i16 -3329>
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; CHECK-NEXT: [[TMP16:%.*]] = icmp slt <2 x i16> [[TMP15]], zeroinitializer
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; CHECK-NEXT: [[TMP17:%.*]] = select <2 x i1> [[TMP16]], <2 x i16> [[TMP14]], <2 x i16> zeroinitializer
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; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[TMP15]], <2 x i16> zeroinitializer)
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; CHECK-NEXT: [[TMP19:%.*]] = or <2 x i16> [[TMP17]], [[TMP18]]
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; CHECK-NEXT: store <2 x i16> [[TMP19]], ptr [[P]], align 2
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; CHECK-NEXT: ret void
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;
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%zext795 = zext i16 %load794 to i32
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%load798 = load i16, ptr %p, align 2
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%gep799 = getelementptr inbounds i8, ptr %p, i64 16
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%load800 = load i16, ptr %gep799, align 2
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%zext801 = zext i16 %load798 to i32
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%zext802 = zext i16 %load800 to i32
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%sub809 = sub nsw i32 %zext802, %zext801
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%add810 = add nsw i32 %sub809, 3329
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%mul811 = mul i32 %add810, %zext795
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%zext812 = zext i32 %mul811 to i64
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%mul813 = mul nuw nsw i64 %zext812, 5039
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%lshr814 = lshr i64 %mul813, 24
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%trunc815 = trunc nuw nsw i64 %lshr814 to i32
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%mul816 = mul i32 %trunc815, 62207
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%add817 = add i32 %mul816, %mul811
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%trunc818 = trunc i32 %add817 to i16
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%add819 = add i16 %trunc818, -3329
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%icmp820 = icmp slt i16 %add819, 0
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%select821 = select i1 %icmp820, i16 %trunc818, i16 0
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%call822 = call i16 @llvm.smax.i16(i16 %add819, i16 0)
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%or823 = or i16 %select821, %call822
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store i16 %or823, ptr %p, align 2
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%gep826 = getelementptr inbounds i8, ptr %p, i64 2
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%load827 = load i16, ptr %gep826, align 2
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%gep828 = getelementptr inbounds i8, ptr %p, i64 18
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%load829 = load i16, ptr %gep828, align 2
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%zext830 = zext i16 %load827 to i32
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%zext831 = zext i16 %load829 to i32
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%sub838 = sub nsw i32 %zext831, %zext830
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%add839 = add nsw i32 %sub838, 3329
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%mul840 = mul i32 %add839, %zext795
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%zext841 = zext i32 %mul840 to i64
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%mul842 = mul nuw nsw i64 %zext841, 5039
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%lshr843 = lshr i64 %mul842, 24
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%trunc844 = trunc nuw nsw i64 %lshr843 to i32
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%mul845 = mul i32 %trunc844, 62207
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%add846 = add i32 %mul845, %mul840
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%trunc847 = trunc i32 %add846 to i16
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%add848 = add i16 %trunc847, -3329
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%icmp849 = icmp slt i16 %add848, 0
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%select850 = select i1 %icmp849, i16 %trunc847, i16 0
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%call851 = call i16 @llvm.smax.i16(i16 %add848, i16 0)
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%or852 = or i16 %select850, %call851
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store i16 %or852, ptr %gep826, align 2
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ret void
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}
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