caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
3fcdd182e9784cb9c2d7ff54b44ec00bd6c91a87
clang-p2996/llvm/test/CodeGen
History
Jay Foad ff7f2cfa95 [AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write 
NFCI. Previously the implicit use was added to V_MOV_B32_indirect_read
when building the instruction. V_MOV_B32_indirect_write didn't have an
implicit use of M0 at all, but apparently it did not cause any problems.

Differential Revision: https://reviews.llvm.org/D114239
2021-11-19 19:00:17 +00:00
..
AArch64
[AARCH64] Teach AArch64FrameLowering::getFrameIndexReferencePreferSP really prefer SP.
2021-11-19 11:14:02 +07:00
AMDGPU
[AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write
2021-11-19 19:00:17 +00:00
ARC
…
ARM
[DAG] MatchRotate - support rotate-by-constant of illegal types
2021-11-19 11:12:04 +00:00
AVR
[asm] Remove explicit branch for modifier 'l'
2021-11-19 09:19:53 -05:00
BPF
BPF: Workaround InstCombine trunc+icmp => mask+icmp Optimization
2021-11-18 20:25:28 -08:00
CSKY
[CSKY] First patch to construct codegen infra and generate first add instruction
2021-11-01 10:06:56 +08:00
Generic
[asm] Correctly handle special names in variants
2021-11-15 15:37:09 -05:00
Hexagon
[LiveIntervals] Update subranges in processTiedPairs
2021-11-11 12:24:59 +00:00
Inputs
…
Lanai
…
M68k
…
Mips
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
MIR
[DebugInfo][NFC] Force some tests to not use instruction-referencing
2021-11-17 11:51:29 +00:00
MSP430
…
NVPTX
[NVPTX] Add imm variants for surface and texture instructions
2021-11-10 19:05:03 +03:00
PowerPC
[PowerPC] Add a flag for conditional trap optimization
2021-11-19 10:24:54 -06:00
RISCV
[RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk
2021-11-19 08:32:59 -08:00
SPARC
[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers
2021-11-14 19:59:52 +01:00
SystemZ
…
Thumb
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
Thumb2
[Thumb2] Regenerate test impacted by e8b55cf7b7.
2021-11-17 11:32:05 +00:00
VE
…
WebAssembly
[WebAssembly] Add prototype relaxed float to int trunc instructions
2021-10-28 14:01:53 -07:00
WinCFGuard
…
WinEH
…
X86
[X86] Selective relocation relaxation for +tagged-globals
2021-11-19 07:18:27 -08:00
XCore
…