a57847232f
The tests in this directory all depend on the AMDGPU target being present so we can let opt infer the data layout. Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137924
150 lines
5.8 KiB
LLVM
150 lines
5.8 KiB
LLVM
; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - %s | FileCheck %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -S -o - %s | FileCheck %s
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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; CHECK-LABEL: @basic_merge_sext_index(
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; CHECK: sext i32 %id.x to i64
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; CHECK: load <2 x float>
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; CHECK: store <2 x float> zeroinitializer
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define amdgpu_kernel void @basic_merge_sext_index(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture %b, ptr addrspace(1) nocapture readonly %c) #0 {
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entry:
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%id.x = call i32 @llvm.amdgcn.workitem.id.x()
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%sext.id.x = sext i32 %id.x to i64
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%a.idx.x = getelementptr inbounds float, ptr addrspace(1) %a, i64 %sext.id.x
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%c.idx.x = getelementptr inbounds float, ptr addrspace(1) %c, i64 %sext.id.x
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%a.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %a.idx.x, i64 1
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%c.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %c.idx.x, i64 1
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%ld.c = load float, ptr addrspace(1) %c.idx.x, align 4
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%ld.c.idx.1 = load float, ptr addrspace(1) %c.idx.x.1, align 4
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store float 0.0, ptr addrspace(1) %a.idx.x, align 4
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store float 0.0, ptr addrspace(1) %a.idx.x.1, align 4
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%add = fadd float %ld.c, %ld.c.idx.1
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store float %add, ptr addrspace(1) %b, align 4
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ret void
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}
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; CHECK-LABEL: @basic_merge_zext_index(
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; CHECK: zext i32 %id.x to i64
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; CHECK: load <2 x float>
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; CHECK: store <2 x float>
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define amdgpu_kernel void @basic_merge_zext_index(ptr addrspace(1) nocapture %a, ptr addrspace(1) nocapture %b, ptr addrspace(1) nocapture readonly %c) #0 {
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entry:
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%id.x = call i32 @llvm.amdgcn.workitem.id.x()
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%zext.id.x = zext i32 %id.x to i64
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%a.idx.x = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x
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%c.idx.x = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x
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%a.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %a.idx.x, i64 1
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%c.idx.x.1 = getelementptr inbounds float, ptr addrspace(1) %c.idx.x, i64 1
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%ld.c = load float, ptr addrspace(1) %c.idx.x, align 4
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%ld.c.idx.1 = load float, ptr addrspace(1) %c.idx.x.1, align 4
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store float 0.0, ptr addrspace(1) %a.idx.x, align 4
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store float 0.0, ptr addrspace(1) %a.idx.x.1, align 4
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%add = fadd float %ld.c, %ld.c.idx.1
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store float %add, ptr addrspace(1) %b, align 4
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ret void
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}
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; CHECK-LABEL: @merge_op_zext_index(
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; CHECK: load <2 x float>
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; CHECK: store <2 x float>
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define amdgpu_kernel void @merge_op_zext_index(ptr addrspace(1) nocapture noalias %a, ptr addrspace(1) nocapture noalias %b, ptr addrspace(1) nocapture readonly noalias %c) #0 {
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entry:
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%id.x = call i32 @llvm.amdgcn.workitem.id.x()
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%shl = shl i32 %id.x, 2
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%zext.id.x = zext i32 %shl to i64
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%a.0 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x
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%c.0 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x
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%id.x.1 = or disjoint i32 %shl, 1
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%id.x.1.ext = zext i32 %id.x.1 to i64
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%a.1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %id.x.1.ext
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%c.1 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %id.x.1.ext
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%ld.c.0 = load float, ptr addrspace(1) %c.0, align 4
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store float 0.0, ptr addrspace(1) %a.0, align 4
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%ld.c.1 = load float, ptr addrspace(1) %c.1, align 4
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store float 0.0, ptr addrspace(1) %a.1, align 4
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%add = fadd float %ld.c.0, %ld.c.1
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store float %add, ptr addrspace(1) %b, align 4
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ret void
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}
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; CHECK-LABEL: @merge_op_sext_index(
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; CHECK: load <2 x float>
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; CHECK: store <2 x float>
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define amdgpu_kernel void @merge_op_sext_index(ptr addrspace(1) nocapture noalias %a, ptr addrspace(1) nocapture noalias %b, ptr addrspace(1) nocapture readonly noalias %c) #0 {
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entry:
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%id.x = call i32 @llvm.amdgcn.workitem.id.x()
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%shl = shl i32 %id.x, 2
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%zext.id.x = sext i32 %shl to i64
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%a.0 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %zext.id.x
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%c.0 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %zext.id.x
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%id.x.1 = or disjoint i32 %shl, 1
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%id.x.1.ext = sext i32 %id.x.1 to i64
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%a.1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 %id.x.1.ext
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%c.1 = getelementptr inbounds float, ptr addrspace(1) %c, i64 %id.x.1.ext
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%ld.c.0 = load float, ptr addrspace(1) %c.0, align 4
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store float 0.0, ptr addrspace(1) %a.0, align 4
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%ld.c.1 = load float, ptr addrspace(1) %c.1, align 4
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store float 0.0, ptr addrspace(1) %a.1, align 4
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%add = fadd float %ld.c.0, %ld.c.1
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store float %add, ptr addrspace(1) %b, align 4
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ret void
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}
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; This case fails to vectorize if not using the extra extension
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; handling in isConsecutiveAccess.
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; CHECK-LABEL: @zext_trunc_phi_1(
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; CHECK: loop:
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; CHECK: load <2 x i32>
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; CHECK: store <2 x i32>
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define amdgpu_kernel void @zext_trunc_phi_1(ptr addrspace(1) nocapture noalias %a, ptr addrspace(1) nocapture noalias %b, ptr addrspace(1) nocapture readonly noalias %c, i32 %n, i64 %arst, i64 %aoeu) #0 {
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entry:
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%cmp0 = icmp eq i32 %n, 0
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br i1 %cmp0, label %exit, label %loop
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loop:
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%indvars.iv = phi i64 [ %indvars.iv.next, %loop ], [ 0, %entry ]
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%trunc.iv = trunc i64 %indvars.iv to i32
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%idx = shl i32 %trunc.iv, 4
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%idx.ext = zext i32 %idx to i64
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%c.0 = getelementptr inbounds i32, ptr addrspace(1) %c, i64 %idx.ext
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%a.0 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %idx.ext
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%idx.1 = or disjoint i32 %idx, 1
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%idx.1.ext = zext i32 %idx.1 to i64
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%c.1 = getelementptr inbounds i32, ptr addrspace(1) %c, i64 %idx.1.ext
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%a.1 = getelementptr inbounds i32, ptr addrspace(1) %a, i64 %idx.1.ext
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%ld.c.0 = load i32, ptr addrspace(1) %c.0, align 4
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store i32 %ld.c.0, ptr addrspace(1) %a.0, align 4
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%ld.c.1 = load i32, ptr addrspace(1) %c.1, align 4
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store i32 %ld.c.1, ptr addrspace(1) %a.1, align 4
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %exit, label %loop
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exit:
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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