This patch updates the RISC-V SpacemiT X60 scheduling model with latency
values collected from the X60 hardware. The previous values were
empirically derived but were slightly off.
Changes:
- LoadLatency (baseline for load instructions): 5 --> 3 cycles
- Memory operations: unified at 4 cycles
- Atomic loads/stores: 5 --> 8 cycles
- Atomic RMW operations: 5 --> 12 cycles
Hardware-measured values provide more accurate instruction scheduling
for the in-order X60 core. Testing shows NFC across benchmarks except
for 523.xalancbmk_r (known to be noisy).
https://lnt.lukelau.me/db_default/v4/nts/663?compare_to=657
3516ad05df