408e55098d
This update enables compress patterns to handle one tied operand in source instructions, which was previously unsupported. Qualcomm's uC extension Xqci includes several instructions with tied operands that can be compressed into smaller forms. This change adds the necessary support to enable such compression. Additionally, a compress pattern for the qc.muliadd instruction has been implemented.
987 lines
42 KiB
C++
987 lines
42 KiB
C++
//===-------- CompressInstEmitter.cpp - Generator for Compression ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// CompressInstEmitter implements a tablegen-driven CompressPat based
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// Instruction Compression mechanism.
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//
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//===----------------------------------------------------------------------===//
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//
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// CompressInstEmitter implements a tablegen-driven CompressPat Instruction
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// Compression mechanism for generating compressed instructions from the
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// expanded instruction form.
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// This tablegen backend processes CompressPat declarations in a
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// td file and generates all the required checks to validate the pattern
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// declarations; validate the input and output operands to generate the correct
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// compressed instructions. The checks include validating different types of
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// operands; register operands, immediate operands, fixed register and fixed
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// immediate inputs.
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//
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// Example:
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// /// Defines a Pat match between compressed and uncompressed instruction.
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// /// The relationship and helper function generation are handled by
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// /// CompressInstEmitter backend.
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// class CompressPat<dag input, dag output, list<Predicate> predicates = []> {
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// /// Uncompressed instruction description.
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// dag Input = input;
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// /// Compressed instruction description.
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// dag Output = output;
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// /// Predicates that must be true for this to match.
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// list<Predicate> Predicates = predicates;
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// /// Duplicate match when tied operand is just different.
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// bit isCompressOnly = false;
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// }
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//
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// let Predicates = [HasStdExtC] in {
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// def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
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// (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
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// }
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//
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// The <TargetName>GenCompressInstEmitter.inc is an auto-generated header
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// file which exports two functions for compressing/uncompressing MCInst
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// instructions, plus some helper functions:
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//
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// bool compressInst(MCInst &OutInst, const MCInst &MI,
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// const MCSubtargetInfo &STI);
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//
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// bool uncompressInst(MCInst &OutInst, const MCInst &MI,
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// const MCSubtargetInfo &STI);
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//
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// In addition, it exports a function for checking whether
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// an instruction is compressable:
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//
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// bool isCompressibleInst(const MachineInstr& MI,
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// const <TargetName>Subtarget &STI);
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//
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// The clients that include this auto-generated header file and
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// invoke these functions can compress an instruction before emitting
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// it in the target-specific ASM or ELF streamer or can uncompress
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// an instruction before printing it when the expanded instruction
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// format aliases is favored.
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//===----------------------------------------------------------------------===//
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#include "Common/CodeGenInstruction.h"
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#include "Common/CodeGenRegisters.h"
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#include "Common/CodeGenTarget.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <limits>
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#include <set>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "compress-inst-emitter"
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namespace {
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class CompressInstEmitter {
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struct OpData {
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enum MapKind { Operand, Imm, Reg };
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MapKind Kind;
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union {
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// Operand number mapped to.
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unsigned Operand;
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// Integer immediate value.
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int64_t Imm;
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// Physical register.
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const Record *Reg;
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} Data;
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// Tied operand index within the instruction.
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int TiedOpIdx = -1;
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};
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struct CompressPat {
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// The source instruction definition.
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CodeGenInstruction Source;
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// The destination instruction to transform to.
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CodeGenInstruction Dest;
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// Required target features to enable pattern.
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std::vector<const Record *> PatReqFeatures;
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// Maps operands in the Source Instruction to
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// the corresponding Dest instruction operand.
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IndexedMap<OpData> SourceOperandMap;
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// Maps operands in the Dest Instruction
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// to the corresponding Source instruction operand.
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IndexedMap<OpData> DestOperandMap;
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bool IsCompressOnly;
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CompressPat(const CodeGenInstruction &S, const CodeGenInstruction &D,
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std::vector<const Record *> RF, IndexedMap<OpData> &SourceMap,
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IndexedMap<OpData> &DestMap, bool IsCompressOnly)
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: Source(S), Dest(D), PatReqFeatures(std::move(RF)),
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SourceOperandMap(SourceMap), DestOperandMap(DestMap),
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IsCompressOnly(IsCompressOnly) {}
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};
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enum EmitterType { Compress, Uncompress, CheckCompress };
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const RecordKeeper &Records;
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const CodeGenTarget Target;
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std::vector<CompressPat> CompressPatterns;
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void addDagOperandMapping(const Record *Rec, const DagInit *Dag,
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const CodeGenInstruction &Inst,
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IndexedMap<OpData> &OperandMap, bool IsSourceInst,
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unsigned *SourceLastTiedOpPtr);
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void evaluateCompressPat(const Record *Compress);
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void emitCompressInstEmitter(raw_ostream &OS, EmitterType EType);
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bool validateTypes(const Record *DagOpType, const Record *InstOpType,
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bool IsSourceInst);
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bool validateRegister(const Record *Reg, const Record *RegClass);
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void createDagOperandMapping(const Record *Rec,
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StringMap<unsigned> &SourceOperands,
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StringMap<unsigned> &DestOperands,
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const DagInit *SourceDag, const DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap);
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void createInstOperandMapping(const Record *Rec, const DagInit *SourceDag,
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const DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap,
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IndexedMap<OpData> &DestOperandMap,
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StringMap<unsigned> &SourceOperands,
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const CodeGenInstruction &DestInst,
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unsigned SourceLastTiedOp);
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public:
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CompressInstEmitter(const RecordKeeper &R) : Records(R), Target(R) {}
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void run(raw_ostream &OS);
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};
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} // End anonymous namespace.
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bool CompressInstEmitter::validateRegister(const Record *Reg,
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const Record *RegClass) {
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assert(Reg->isSubClassOf("Register") && "Reg record should be a Register");
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assert(RegClass->isSubClassOf("RegisterClass") &&
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"RegClass record should be a RegisterClass");
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const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
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const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
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assert(R != nullptr && "Register not defined!!");
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return RC.contains(R);
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}
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bool CompressInstEmitter::validateTypes(const Record *DagOpType,
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const Record *InstOpType,
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bool IsSourceInst) {
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if (DagOpType == InstOpType)
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return true;
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// Only source instruction operands are allowed to not match Input Dag
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// operands.
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if (!IsSourceInst)
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return false;
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if (DagOpType->isSubClassOf("RegisterClass") &&
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InstOpType->isSubClassOf("RegisterClass")) {
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const CodeGenRegisterClass &RC = Target.getRegisterClass(InstOpType);
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const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType);
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return RC.hasSubClass(&SubRC);
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}
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// At this point either or both types are not registers, reject the pattern.
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if (DagOpType->isSubClassOf("RegisterClass") ||
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InstOpType->isSubClassOf("RegisterClass"))
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return false;
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// Let further validation happen when compress()/uncompress() functions are
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// invoked.
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LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output")
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<< " Dag Operand Type: '" << DagOpType->getName()
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<< "' and "
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<< "Instruction Operand Type: '" << InstOpType->getName()
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<< "' can't be checked at pattern validation time!\n");
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return true;
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}
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/// The patterns in the Dag contain different types of operands:
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/// Register operands, e.g.: GPRC:$rs1; Fixed registers, e.g: X1; Immediate
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/// operands, e.g.: simm6:$imm; Fixed immediate operands, e.g.: 0. This function
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/// maps Dag operands to its corresponding instruction operands. For register
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/// operands and fixed registers it expects the Dag operand type to be contained
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/// in the instantiated instruction operand type. For immediate operands and
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/// immediates no validation checks are enforced at pattern validation time.
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void CompressInstEmitter::addDagOperandMapping(const Record *Rec,
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const DagInit *Dag,
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const CodeGenInstruction &Inst,
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IndexedMap<OpData> &OperandMap,
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bool IsSourceInst,
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unsigned *SourceLastTiedOpPtr) {
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unsigned NumMIOperands = 0;
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for (const auto &Op : Inst.Operands)
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NumMIOperands += Op.MINumOperands;
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OperandMap.grow(NumMIOperands);
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// TiedCount keeps track of the number of operands skipped in Inst
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// operands list to get to the corresponding Dag operand. This is
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// necessary because the number of operands in Inst might be greater
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// than number of operands in the Dag due to how tied operands
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// are represented.
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unsigned TiedCount = 0;
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unsigned OpNo = 0;
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if (IsSourceInst)
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*SourceLastTiedOpPtr = std::numeric_limits<unsigned int>::max();
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for (const auto &Opnd : Inst.Operands) {
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int TiedOpIdx = Opnd.getTiedRegister();
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if (-1 != TiedOpIdx) {
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// Set the entry in OperandMap for the tied operand we're skipping.
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OperandMap[OpNo].Kind = OperandMap[TiedOpIdx].Kind;
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OperandMap[OpNo].Data = OperandMap[TiedOpIdx].Data;
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if (IsSourceInst)
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*SourceLastTiedOpPtr = OpNo;
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++OpNo;
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++TiedCount;
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continue;
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}
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for (unsigned SubOp = 0; SubOp != Opnd.MINumOperands; ++SubOp, ++OpNo) {
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unsigned DAGOpNo = OpNo - TiedCount;
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const Record *OpndRec = Opnd.Rec;
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if (Opnd.MINumOperands > 1)
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OpndRec = cast<DefInit>(Opnd.MIOperandInfo->getArg(SubOp))->getDef();
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if (const auto *DI = dyn_cast<DefInit>(Dag->getArg(DAGOpNo))) {
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if (DI->getDef()->isSubClassOf("Register")) {
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// Check if the fixed register belongs to the Register class.
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if (!validateRegister(DI->getDef(), OpndRec))
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PrintFatalError(Rec->getLoc(),
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"Error in Dag '" + Dag->getAsString() +
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"'Register: '" + DI->getDef()->getName() +
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"' is not in register class '" +
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OpndRec->getName() + "'");
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OperandMap[OpNo].Kind = OpData::Reg;
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OperandMap[OpNo].Data.Reg = DI->getDef();
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continue;
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}
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// Validate that Dag operand type matches the type defined in the
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// corresponding instruction. Operands in the input Dag pattern are
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// allowed to be a subclass of the type specified in corresponding
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// instruction operand instead of being an exact match.
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if (!validateTypes(DI->getDef(), OpndRec, IsSourceInst))
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PrintFatalError(Rec->getLoc(),
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"Error in Dag '" + Dag->getAsString() +
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"'. Operand '" + Dag->getArgNameStr(DAGOpNo) +
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"' has type '" + DI->getDef()->getName() +
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"' which does not match the type '" +
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OpndRec->getName() +
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"' in the corresponding instruction operand!");
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OperandMap[OpNo].Kind = OpData::Operand;
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} else if (const auto *II = dyn_cast<IntInit>(Dag->getArg(DAGOpNo))) {
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// Validate that corresponding instruction operand expects an immediate.
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if (OpndRec->isSubClassOf("RegisterClass"))
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PrintFatalError(Rec->getLoc(), "Error in Dag '" + Dag->getAsString() +
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"' Found immediate: '" +
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II->getAsString() +
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"' but corresponding instruction "
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"operand expected a register!");
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// No pattern validation check possible for values of fixed immediate.
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OperandMap[OpNo].Kind = OpData::Imm;
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OperandMap[OpNo].Data.Imm = II->getValue();
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LLVM_DEBUG(
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dbgs() << " Found immediate '" << II->getValue() << "' at "
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<< (IsSourceInst ? "input " : "output ")
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<< "Dag. No validation time check possible for values of "
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"fixed immediate.\n");
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} else {
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llvm_unreachable("Unhandled CompressPat argument type!");
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}
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}
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}
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}
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// Verify the Dag operand count is enough to build an instruction.
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static bool verifyDagOpCount(const CodeGenInstruction &Inst, const DagInit *Dag,
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bool IsSource) {
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unsigned NumMIOperands = 0;
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// Use this to count number of tied Operands in Source Inst in this function.
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// This counter is required here to error out when there is a Source
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// Inst with two or more tied operands.
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unsigned SourceInstTiedOpCount = 0;
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for (const auto &Op : Inst.Operands) {
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NumMIOperands += Op.MINumOperands;
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if (Op.getTiedRegister() != -1)
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SourceInstTiedOpCount++;
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}
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if (Dag->getNumArgs() == NumMIOperands)
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return true;
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// Source instructions are non compressed instructions and have at most one
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// tied operand.
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if (IsSource && (SourceInstTiedOpCount >= 2))
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PrintFatalError(Inst.TheDef->getLoc(),
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"Input operands for Inst '" + Inst.TheDef->getName() +
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"' and input Dag operand count mismatch");
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// The Dag can't have more arguments than the Instruction.
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if (Dag->getNumArgs() > NumMIOperands)
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PrintFatalError(Inst.TheDef->getLoc(),
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"Inst '" + Inst.TheDef->getName() +
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"' and Dag operand count mismatch");
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// The Instruction might have tied operands so the Dag might have
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// a fewer operand count.
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unsigned RealCount = NumMIOperands;
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for (const auto &Operand : Inst.Operands)
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if (Operand.getTiedRegister() != -1)
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--RealCount;
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if (Dag->getNumArgs() != RealCount)
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PrintFatalError(Inst.TheDef->getLoc(),
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"Inst '" + Inst.TheDef->getName() +
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"' and Dag operand count mismatch");
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return true;
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}
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static bool validateArgsTypes(const Init *Arg1, const Init *Arg2) {
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return cast<DefInit>(Arg1)->getDef() == cast<DefInit>(Arg2)->getDef();
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}
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// Creates a mapping between the operand name in the Dag (e.g. $rs1) and
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// its index in the list of Dag operands and checks that operands with the same
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// name have the same types. For example in 'C_ADD $rs1, $rs2' we generate the
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// mapping $rs1 --> 0, $rs2 ---> 1. If the operand appears twice in the (tied)
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// same Dag we use the last occurrence for indexing.
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void CompressInstEmitter::createDagOperandMapping(
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const Record *Rec, StringMap<unsigned> &SourceOperands,
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StringMap<unsigned> &DestOperands, const DagInit *SourceDag,
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const DagInit *DestDag, IndexedMap<OpData> &SourceOperandMap) {
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for (unsigned I = 0; I < DestDag->getNumArgs(); ++I) {
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// Skip fixed immediates and registers, they were handled in
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// addDagOperandMapping.
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if ("" == DestDag->getArgNameStr(I))
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continue;
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DestOperands[DestDag->getArgNameStr(I)] = I;
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}
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for (unsigned I = 0; I < SourceDag->getNumArgs(); ++I) {
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// Skip fixed immediates and registers, they were handled in
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// addDagOperandMapping.
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if ("" == SourceDag->getArgNameStr(I))
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continue;
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StringMap<unsigned>::iterator It =
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SourceOperands.find(SourceDag->getArgNameStr(I));
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if (It != SourceOperands.end()) {
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// Operand sharing the same name in the Dag should be mapped as tied.
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SourceOperandMap[I].TiedOpIdx = It->getValue();
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if (!validateArgsTypes(SourceDag->getArg(It->getValue()),
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SourceDag->getArg(I)))
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PrintFatalError(Rec->getLoc(),
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"Input Operand '" + SourceDag->getArgNameStr(I) +
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"' has a mismatched tied operand!\n");
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}
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It = DestOperands.find(SourceDag->getArgNameStr(I));
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if (It == DestOperands.end())
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PrintFatalError(Rec->getLoc(), "Operand " + SourceDag->getArgNameStr(I) +
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" defined in Input Dag but not used in"
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" Output Dag!\n");
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// Input Dag operand types must match output Dag operand type.
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if (!validateArgsTypes(DestDag->getArg(It->getValue()),
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SourceDag->getArg(I)))
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PrintFatalError(Rec->getLoc(), "Type mismatch between Input and "
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"Output Dag operand '" +
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SourceDag->getArgNameStr(I) + "'!");
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SourceOperands[SourceDag->getArgNameStr(I)] = I;
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}
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}
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/// Map operand names in the Dag to their index in both corresponding input and
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/// output instructions. Validate that operands defined in the input are
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/// used in the output pattern while populating the maps.
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void CompressInstEmitter::createInstOperandMapping(
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const Record *Rec, const DagInit *SourceDag, const DagInit *DestDag,
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IndexedMap<OpData> &SourceOperandMap, IndexedMap<OpData> &DestOperandMap,
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StringMap<unsigned> &SourceOperands, const CodeGenInstruction &DestInst,
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unsigned SourceLastTiedOp) {
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// TiedCount keeps track of the number of operands skipped in Inst
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// operands list to get to the corresponding Dag operand.
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unsigned TiedCount = 0;
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LLVM_DEBUG(dbgs() << " Operand mapping:\n Source Dest\n");
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unsigned OpNo = 0;
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for (const auto &Operand : DestInst.Operands) {
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int TiedInstOpIdx = Operand.getTiedRegister();
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if (TiedInstOpIdx != -1) {
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++TiedCount;
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DestOperandMap[OpNo].Data = DestOperandMap[TiedInstOpIdx].Data;
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DestOperandMap[OpNo].Kind = DestOperandMap[TiedInstOpIdx].Kind;
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if (DestOperandMap[OpNo].Kind == OpData::Operand)
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// No need to fill the SourceOperandMap here since it was mapped to
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// destination operand 'TiedInstOpIdx' in a previous iteration.
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LLVM_DEBUG(dbgs() << " " << DestOperandMap[OpNo].Data.Operand
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<< " ====> " << OpNo
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<< " Dest operand tied with operand '"
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<< TiedInstOpIdx << "'\n");
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++OpNo;
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continue;
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}
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for (unsigned SubOp = 0; SubOp != Operand.MINumOperands; ++SubOp, ++OpNo) {
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// Skip fixed immediates and registers, they were handled in
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// addDagOperandMapping.
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if (DestOperandMap[OpNo].Kind != OpData::Operand)
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continue;
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unsigned DagArgIdx = OpNo - TiedCount;
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StringMap<unsigned>::iterator SourceOp =
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SourceOperands.find(DestDag->getArgNameStr(DagArgIdx));
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if (SourceOp == SourceOperands.end())
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PrintFatalError(Rec->getLoc(),
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"Output Dag operand '" +
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DestDag->getArgNameStr(DagArgIdx) +
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"' has no matching input Dag operand.");
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assert(DestDag->getArgNameStr(DagArgIdx) ==
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SourceDag->getArgNameStr(SourceOp->getValue()) &&
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"Incorrect operand mapping detected!\n");
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// Following four lines ensure the correct handling of a single tied
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|
// operand in the Source Inst. SourceDagOp points to the position of
|
|
// appropriate Dag argument which is not correct in presence of tied
|
|
// operand in the Source Inst and must be incremented by 1 to reflect
|
|
// correct position of the operand in Source Inst
|
|
unsigned SourceDagOp = SourceOp->getValue();
|
|
if (SourceDagOp >= SourceLastTiedOp)
|
|
SourceDagOp++;
|
|
DestOperandMap[OpNo].Data.Operand = SourceDagOp;
|
|
SourceOperandMap[SourceDagOp].Data.Operand = OpNo;
|
|
LLVM_DEBUG(dbgs() << " " << SourceDagOp << " ====> " << OpNo << "\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Validates the CompressPattern and create operand mapping.
|
|
/// These are the checks to validate a CompressPat pattern declarations.
|
|
/// Error out with message under these conditions:
|
|
/// - Dag Input opcode is an expanded instruction and Dag Output opcode is a
|
|
/// compressed instruction.
|
|
/// - Operands in Dag Input must be all used in Dag Output.
|
|
/// Register Operand type in Dag Input Type must be contained in the
|
|
/// corresponding Source Instruction type.
|
|
/// - Register Operand type in Dag Input must be the same as in Dag Ouput.
|
|
/// - Register Operand type in Dag Output must be the same as the
|
|
/// corresponding Destination Inst type.
|
|
/// - Immediate Operand type in Dag Input must be the same as in Dag Ouput.
|
|
/// - Immediate Operand type in Dag Ouput must be the same as the corresponding
|
|
/// Destination Instruction type.
|
|
/// - Fixed register must be contained in the corresponding Source Instruction
|
|
/// type.
|
|
/// - Fixed register must be contained in the corresponding Destination
|
|
/// Instruction type.
|
|
/// Warning message printed under these conditions:
|
|
/// - Fixed immediate in Dag Input or Dag Ouput cannot be checked at this time
|
|
/// and generate warning.
|
|
/// - Immediate operand type in Dag Input differs from the corresponding Source
|
|
/// Instruction type and generate a warning.
|
|
void CompressInstEmitter::evaluateCompressPat(const Record *Rec) {
|
|
// Validate input Dag operands.
|
|
const DagInit *SourceDag = Rec->getValueAsDag("Input");
|
|
assert(SourceDag && "Missing 'Input' in compress pattern!");
|
|
LLVM_DEBUG(dbgs() << "Input: " << *SourceDag << "\n");
|
|
|
|
// Checking we are transforming from compressed to uncompressed instructions.
|
|
const Record *SourceOperator = SourceDag->getOperatorAsDef(Rec->getLoc());
|
|
CodeGenInstruction SourceInst(SourceOperator);
|
|
verifyDagOpCount(SourceInst, SourceDag, true);
|
|
|
|
// Validate output Dag operands.
|
|
const DagInit *DestDag = Rec->getValueAsDag("Output");
|
|
assert(DestDag && "Missing 'Output' in compress pattern!");
|
|
LLVM_DEBUG(dbgs() << "Output: " << *DestDag << "\n");
|
|
|
|
const Record *DestOperator = DestDag->getOperatorAsDef(Rec->getLoc());
|
|
CodeGenInstruction DestInst(DestOperator);
|
|
verifyDagOpCount(DestInst, DestDag, false);
|
|
|
|
if (SourceOperator->getValueAsInt("Size") <=
|
|
DestOperator->getValueAsInt("Size"))
|
|
PrintFatalError(
|
|
Rec->getLoc(),
|
|
"Compressed instruction '" + DestOperator->getName() +
|
|
"'is not strictly smaller than the uncompressed instruction '" +
|
|
SourceOperator->getName() + "' !");
|
|
|
|
// Fill the mapping from the source to destination instructions.
|
|
|
|
IndexedMap<OpData> SourceOperandMap;
|
|
unsigned SourceLastTiedOp; // postion of the last tied operand in Source Inst
|
|
// Create a mapping between source Dag operands and source Inst operands.
|
|
addDagOperandMapping(Rec, SourceDag, SourceInst, SourceOperandMap,
|
|
/*IsSourceInst*/ true, &SourceLastTiedOp);
|
|
|
|
IndexedMap<OpData> DestOperandMap;
|
|
// Create a mapping between destination Dag operands and destination Inst
|
|
// operands.
|
|
addDagOperandMapping(Rec, DestDag, DestInst, DestOperandMap,
|
|
/*IsSourceInst*/ false, nullptr);
|
|
|
|
StringMap<unsigned> SourceOperands;
|
|
StringMap<unsigned> DestOperands;
|
|
createDagOperandMapping(Rec, SourceOperands, DestOperands, SourceDag, DestDag,
|
|
SourceOperandMap);
|
|
// Create operand mapping between the source and destination instructions.
|
|
createInstOperandMapping(Rec, SourceDag, DestDag, SourceOperandMap,
|
|
DestOperandMap, SourceOperands, DestInst,
|
|
SourceLastTiedOp);
|
|
|
|
// Get the target features for the CompressPat.
|
|
std::vector<const Record *> PatReqFeatures;
|
|
std::vector<const Record *> RF = Rec->getValueAsListOfDefs("Predicates");
|
|
copy_if(RF, std::back_inserter(PatReqFeatures), [](const Record *R) {
|
|
return R->getValueAsBit("AssemblerMatcherPredicate");
|
|
});
|
|
|
|
CompressPatterns.push_back(CompressPat(
|
|
SourceInst, DestInst, std::move(PatReqFeatures), SourceOperandMap,
|
|
DestOperandMap, Rec->getValueAsBit("isCompressOnly")));
|
|
}
|
|
|
|
static void
|
|
getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
|
|
std::set<std::set<std::pair<bool, StringRef>>> &AnyOfFeatureSets,
|
|
ArrayRef<const Record *> ReqFeatures) {
|
|
for (const Record *R : ReqFeatures) {
|
|
const DagInit *D = R->getValueAsDag("AssemblerCondDag");
|
|
std::string CombineType = D->getOperator()->getAsString();
|
|
if (CombineType != "any_of" && CombineType != "all_of")
|
|
PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
|
|
if (D->getNumArgs() == 0)
|
|
PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
|
|
bool IsOr = CombineType == "any_of";
|
|
std::set<std::pair<bool, StringRef>> AnyOfSet;
|
|
|
|
for (auto *Arg : D->getArgs()) {
|
|
bool IsNot = false;
|
|
if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
|
|
if (NotArg->getOperator()->getAsString() != "not" ||
|
|
NotArg->getNumArgs() != 1)
|
|
PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
|
|
Arg = NotArg->getArg(0);
|
|
IsNot = true;
|
|
}
|
|
if (!isa<DefInit>(Arg) ||
|
|
!cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
|
|
PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
|
|
if (IsOr)
|
|
AnyOfSet.emplace(IsNot, cast<DefInit>(Arg)->getDef()->getName());
|
|
else
|
|
FeaturesSet.emplace(IsNot, cast<DefInit>(Arg)->getDef()->getName());
|
|
}
|
|
|
|
if (IsOr)
|
|
AnyOfFeatureSets.insert(std::move(AnyOfSet));
|
|
}
|
|
}
|
|
|
|
static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
|
|
std::vector<const Record *> &Predicates,
|
|
const Record *Rec, StringRef Name) {
|
|
unsigned &Entry = PredicateMap[Rec];
|
|
if (Entry)
|
|
return Entry;
|
|
|
|
if (!Rec->isValueUnset(Name)) {
|
|
Predicates.push_back(Rec);
|
|
Entry = Predicates.size();
|
|
return Entry;
|
|
}
|
|
|
|
PrintFatalError(Rec->getLoc(), "No " + Name +
|
|
" predicate on this operand at all: '" +
|
|
Rec->getName() + "'");
|
|
return 0;
|
|
}
|
|
|
|
static void printPredicates(ArrayRef<const Record *> Predicates, StringRef Name,
|
|
raw_ostream &OS) {
|
|
for (unsigned I = 0; I < Predicates.size(); ++I) {
|
|
StringRef Pred = Predicates[I]->getValueAsString(Name);
|
|
Pred = Pred.trim();
|
|
OS.indent(2) << "case " << I + 1 << ": {\n";
|
|
OS.indent(4) << "// " << Predicates[I]->getName() << "\n";
|
|
OS.indent(4) << Pred << "\n";
|
|
OS.indent(2) << "}\n";
|
|
}
|
|
}
|
|
|
|
static void mergeCondAndCode(raw_ostream &CombinedStream, StringRef CondStr,
|
|
StringRef CodeStr) {
|
|
// Remove first indentation and last '&&'.
|
|
CondStr = CondStr.drop_front(8).drop_back(4);
|
|
CombinedStream.indent(4) << "if (" << CondStr << ") {\n";
|
|
CombinedStream << CodeStr;
|
|
CombinedStream.indent(4) << " return true;\n";
|
|
CombinedStream.indent(4) << "} // if\n";
|
|
}
|
|
|
|
void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS,
|
|
EmitterType EType) {
|
|
const Record *AsmWriter = Target.getAsmWriter();
|
|
if (!AsmWriter->getValueAsInt("PassSubtarget"))
|
|
PrintFatalError(AsmWriter->getLoc(),
|
|
"'PassSubtarget' is false. SubTargetInfo object is needed "
|
|
"for target features.\n");
|
|
|
|
StringRef TargetName = Target.getName();
|
|
|
|
// Sort entries in CompressPatterns to handle instructions that can have more
|
|
// than one candidate for compression\uncompression, e.g ADD can be
|
|
// transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function the
|
|
// source and destination are flipped and the sort key needs to change
|
|
// accordingly.
|
|
llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
|
|
const CompressPat &RHS) {
|
|
if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
|
|
return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
|
|
return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
|
|
});
|
|
|
|
// A list of MCOperandPredicates for all operands in use, and the reverse map.
|
|
std::vector<const Record *> MCOpPredicates;
|
|
DenseMap<const Record *, unsigned> MCOpPredicateMap;
|
|
// A list of ImmLeaf Predicates for all operands in use, and the reverse map.
|
|
std::vector<const Record *> ImmLeafPredicates;
|
|
DenseMap<const Record *, unsigned> ImmLeafPredicateMap;
|
|
|
|
std::string F;
|
|
std::string FH;
|
|
raw_string_ostream Func(F);
|
|
raw_string_ostream FuncH(FH);
|
|
|
|
if (EType == EmitterType::Compress)
|
|
OS << "\n#ifdef GEN_COMPRESS_INSTR\n"
|
|
<< "#undef GEN_COMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::Uncompress)
|
|
OS << "\n#ifdef GEN_UNCOMPRESS_INSTR\n"
|
|
<< "#undef GEN_UNCOMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::CheckCompress)
|
|
OS << "\n#ifdef GEN_CHECK_COMPRESS_INSTR\n"
|
|
<< "#undef GEN_CHECK_COMPRESS_INSTR\n\n";
|
|
|
|
if (EType == EmitterType::Compress) {
|
|
FuncH << "static bool compressInst(MCInst &OutInst,\n";
|
|
FuncH.indent(25) << "const MCInst &MI,\n";
|
|
FuncH.indent(25) << "const MCSubtargetInfo &STI) {\n";
|
|
} else if (EType == EmitterType::Uncompress) {
|
|
FuncH << "static bool uncompressInst(MCInst &OutInst,\n";
|
|
FuncH.indent(27) << "const MCInst &MI,\n";
|
|
FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
|
|
} else if (EType == EmitterType::CheckCompress) {
|
|
FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
|
|
FuncH.indent(31) << "const " << TargetName << "Subtarget &STI) {\n";
|
|
}
|
|
|
|
if (CompressPatterns.empty()) {
|
|
OS << FH;
|
|
OS.indent(2) << "return false;\n}\n";
|
|
if (EType == EmitterType::Compress)
|
|
OS << "\n#endif //GEN_COMPRESS_INSTR\n";
|
|
else if (EType == EmitterType::Uncompress)
|
|
OS << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::CheckCompress)
|
|
OS << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n";
|
|
return;
|
|
}
|
|
|
|
std::string CaseString;
|
|
raw_string_ostream CaseStream(CaseString);
|
|
StringRef PrevOp;
|
|
StringRef CurOp;
|
|
CaseStream << " switch (MI.getOpcode()) {\n";
|
|
CaseStream << " default: return false;\n";
|
|
|
|
bool CompressOrCheck =
|
|
EType == EmitterType::Compress || EType == EmitterType::CheckCompress;
|
|
bool CompressOrUncompress =
|
|
EType == EmitterType::Compress || EType == EmitterType::Uncompress;
|
|
std::string ValidatorName =
|
|
CompressOrUncompress
|
|
? (TargetName + "ValidateMCOperandFor" +
|
|
(EType == EmitterType::Compress ? "Compress" : "Uncompress"))
|
|
.str()
|
|
: "";
|
|
|
|
for (auto &CompressPat : CompressPatterns) {
|
|
if (EType == EmitterType::Uncompress && CompressPat.IsCompressOnly)
|
|
continue;
|
|
|
|
std::string CondString;
|
|
std::string CodeString;
|
|
raw_string_ostream CondStream(CondString);
|
|
raw_string_ostream CodeStream(CodeString);
|
|
CodeGenInstruction &Source =
|
|
CompressOrCheck ? CompressPat.Source : CompressPat.Dest;
|
|
CodeGenInstruction &Dest =
|
|
CompressOrCheck ? CompressPat.Dest : CompressPat.Source;
|
|
IndexedMap<OpData> SourceOperandMap = CompressOrCheck
|
|
? CompressPat.SourceOperandMap
|
|
: CompressPat.DestOperandMap;
|
|
IndexedMap<OpData> &DestOperandMap = CompressOrCheck
|
|
? CompressPat.DestOperandMap
|
|
: CompressPat.SourceOperandMap;
|
|
|
|
CurOp = Source.TheDef->getName();
|
|
// Check current and previous opcode to decide to continue or end a case.
|
|
if (CurOp != PrevOp) {
|
|
if (!PrevOp.empty())
|
|
CaseStream.indent(6) << "break;\n } // case " + PrevOp + "\n";
|
|
CaseStream.indent(4) << "case " + TargetName + "::" + CurOp + ": {\n";
|
|
}
|
|
|
|
std::set<std::pair<bool, StringRef>> FeaturesSet;
|
|
std::set<std::set<std::pair<bool, StringRef>>> AnyOfFeatureSets;
|
|
// Add CompressPat required features.
|
|
getReqFeatures(FeaturesSet, AnyOfFeatureSets, CompressPat.PatReqFeatures);
|
|
|
|
// Add Dest instruction required features.
|
|
std::vector<const Record *> ReqFeatures;
|
|
std::vector<const Record *> RF =
|
|
Dest.TheDef->getValueAsListOfDefs("Predicates");
|
|
copy_if(RF, std::back_inserter(ReqFeatures), [](const Record *R) {
|
|
return R->getValueAsBit("AssemblerMatcherPredicate");
|
|
});
|
|
getReqFeatures(FeaturesSet, AnyOfFeatureSets, ReqFeatures);
|
|
|
|
// Emit checks for all required features.
|
|
for (auto &Op : FeaturesSet) {
|
|
StringRef Not = Op.first ? "!" : "";
|
|
CondStream.indent(8) << Not << "STI.getFeatureBits()[" << TargetName
|
|
<< "::" << Op.second << "]"
|
|
<< " &&\n";
|
|
}
|
|
|
|
// Emit checks for all required feature groups.
|
|
for (auto &Set : AnyOfFeatureSets) {
|
|
CondStream.indent(8) << "(";
|
|
for (auto &Op : Set) {
|
|
bool IsLast = &Op == &*Set.rbegin();
|
|
StringRef Not = Op.first ? "!" : "";
|
|
CondStream << Not << "STI.getFeatureBits()[" << TargetName
|
|
<< "::" << Op.second << "]";
|
|
if (!IsLast)
|
|
CondStream << " || ";
|
|
}
|
|
CondStream << ") &&\n";
|
|
}
|
|
|
|
// Start Source Inst operands validation.
|
|
unsigned OpNo = 0;
|
|
for (const auto &SourceOperand : Source.Operands) {
|
|
if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
|
|
if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
|
|
CondStream.indent(8)
|
|
<< "(MI.getOperand(" << OpNo << ").isReg()) && (MI.getOperand("
|
|
<< SourceOperandMap[OpNo].TiedOpIdx << ").isReg()) &&\n"
|
|
<< indent(8) << "(MI.getOperand(" << OpNo
|
|
<< ").getReg() == MI.getOperand("
|
|
<< SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
|
|
else
|
|
PrintFatalError("Unexpected tied operand types!\n");
|
|
}
|
|
for (unsigned SubOp = 0; SubOp != SourceOperand.MINumOperands; ++SubOp) {
|
|
// Check for fixed immediates\registers in the source instruction.
|
|
switch (SourceOperandMap[OpNo].Kind) {
|
|
case OpData::Operand:
|
|
// We don't need to do anything for source instruction operand checks.
|
|
break;
|
|
case OpData::Imm:
|
|
CondStream.indent(8)
|
|
<< "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
|
|
<< " (MI.getOperand(" << OpNo
|
|
<< ").getImm() == " << SourceOperandMap[OpNo].Data.Imm
|
|
<< ") &&\n";
|
|
break;
|
|
case OpData::Reg: {
|
|
const Record *Reg = SourceOperandMap[OpNo].Data.Reg;
|
|
CondStream.indent(8) << "(MI.getOperand(" << OpNo << ").isReg()) &&\n"
|
|
<< indent(8) << "(MI.getOperand(" << OpNo
|
|
<< ").getReg() == " << TargetName
|
|
<< "::" << Reg->getName() << ") &&\n";
|
|
break;
|
|
}
|
|
}
|
|
++OpNo;
|
|
}
|
|
}
|
|
CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.setOpcode(" << TargetName
|
|
<< "::" << Dest.TheDef->getName() << ");\n";
|
|
OpNo = 0;
|
|
for (const auto &DestOperand : Dest.Operands) {
|
|
CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
|
|
|
|
for (unsigned SubOp = 0; SubOp != DestOperand.MINumOperands; ++SubOp) {
|
|
const Record *DestRec = DestOperand.Rec;
|
|
|
|
if (DestOperand.MINumOperands > 1)
|
|
DestRec =
|
|
cast<DefInit>(DestOperand.MIOperandInfo->getArg(SubOp))->getDef();
|
|
|
|
switch (DestOperandMap[OpNo].Kind) {
|
|
case OpData::Operand: {
|
|
unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
|
|
// Check that the operand in the Source instruction fits
|
|
// the type for the Dest instruction.
|
|
if (DestRec->isSubClassOf("RegisterClass") ||
|
|
DestRec->isSubClassOf("RegisterOperand")) {
|
|
auto *ClassRec = DestRec->isSubClassOf("RegisterClass")
|
|
? DestRec
|
|
: DestRec->getValueAsDef("RegClass");
|
|
// This is a register operand. Check the register class.
|
|
// Don't check register class if this is a tied operand, it was done
|
|
// for the operand its tied to.
|
|
if (DestOperand.getTiedRegister() == -1) {
|
|
CondStream.indent(8) << "MI.getOperand(" << OpIdx << ").isReg()";
|
|
if (EType == EmitterType::CheckCompress)
|
|
CondStream << " && MI.getOperand(" << OpIdx
|
|
<< ").getReg().isPhysical()";
|
|
CondStream << " &&\n"
|
|
<< indent(8) << TargetName << "MCRegisterClasses["
|
|
<< TargetName << "::" << ClassRec->getName()
|
|
<< "RegClassID].contains(MI.getOperand(" << OpIdx
|
|
<< ").getReg()) &&\n";
|
|
}
|
|
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6)
|
|
<< "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
|
|
} else {
|
|
// Handling immediate operands.
|
|
if (CompressOrUncompress) {
|
|
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
|
|
DestRec, "MCOperandPredicate");
|
|
CondStream.indent(8) << ValidatorName << "("
|
|
<< "MI.getOperand(" << OpIdx << "), STI, "
|
|
<< Entry << ") &&\n";
|
|
} else {
|
|
unsigned Entry =
|
|
getPredicates(ImmLeafPredicateMap, ImmLeafPredicates, DestRec,
|
|
"ImmediateCode");
|
|
CondStream.indent(8)
|
|
<< "MI.getOperand(" << OpIdx << ").isImm() &&\n";
|
|
CondStream.indent(8) << TargetName << "ValidateMachineOperand("
|
|
<< "MI.getOperand(" << OpIdx << "), &STI, "
|
|
<< Entry << ") &&\n";
|
|
}
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6)
|
|
<< "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
|
|
}
|
|
break;
|
|
}
|
|
case OpData::Imm: {
|
|
if (CompressOrUncompress) {
|
|
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
|
|
DestRec, "MCOperandPredicate");
|
|
CondStream.indent(8)
|
|
<< ValidatorName << "("
|
|
<< "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
|
|
<< "), STI, " << Entry << ") &&\n";
|
|
} else {
|
|
unsigned Entry =
|
|
getPredicates(ImmLeafPredicateMap, ImmLeafPredicates, DestRec,
|
|
"ImmediateCode");
|
|
CondStream.indent(8)
|
|
<< TargetName
|
|
<< "ValidateMachineOperand(MachineOperand::CreateImm("
|
|
<< DestOperandMap[OpNo].Data.Imm << "), &STI, " << Entry
|
|
<< ") &&\n";
|
|
}
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("
|
|
<< DestOperandMap[OpNo].Data.Imm << "));\n";
|
|
} break;
|
|
case OpData::Reg: {
|
|
if (CompressOrUncompress) {
|
|
// Fixed register has been validated at pattern validation time.
|
|
const Record *Reg = DestOperandMap[OpNo].Data.Reg;
|
|
CodeStream.indent(6)
|
|
<< "OutInst.addOperand(MCOperand::createReg(" << TargetName
|
|
<< "::" << Reg->getName() << "));\n";
|
|
}
|
|
} break;
|
|
}
|
|
++OpNo;
|
|
}
|
|
}
|
|
if (CompressOrUncompress)
|
|
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
|
|
mergeCondAndCode(CaseStream, CondString, CodeString);
|
|
PrevOp = CurOp;
|
|
}
|
|
Func << CaseString << "\n";
|
|
// Close brace for the last case.
|
|
Func.indent(4) << "} // case " << CurOp << "\n";
|
|
Func.indent(2) << "} // switch\n";
|
|
Func.indent(2) << "return false;\n}\n";
|
|
|
|
if (!MCOpPredicates.empty()) {
|
|
auto IndentLength = ValidatorName.size() + 13;
|
|
OS << "static bool " << ValidatorName << "(const MCOperand &MCOp,\n";
|
|
OS.indent(IndentLength) << "const MCSubtargetInfo &STI,\n";
|
|
OS.indent(IndentLength) << "unsigned PredicateIndex) {\n";
|
|
OS << " switch (PredicateIndex) {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
|
|
<< " break;\n";
|
|
|
|
printPredicates(MCOpPredicates, "MCOperandPredicate", OS);
|
|
|
|
OS << " }\n"
|
|
<< "}\n\n";
|
|
}
|
|
|
|
if (!ImmLeafPredicates.empty()) {
|
|
auto IndentLength = TargetName.size() + 35;
|
|
OS << "static bool " << TargetName
|
|
<< "ValidateMachineOperand(const MachineOperand &MO,\n";
|
|
OS.indent(IndentLength)
|
|
<< "const " << TargetName << "Subtarget *Subtarget,\n";
|
|
OS.indent(IndentLength)
|
|
<< "unsigned PredicateIndex) {\n"
|
|
<< " int64_t Imm = MO.getImm();\n"
|
|
<< " switch (PredicateIndex) {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n"
|
|
<< " break;\n";
|
|
|
|
printPredicates(ImmLeafPredicates, "ImmediateCode", OS);
|
|
|
|
OS << " }\n"
|
|
<< "}\n\n";
|
|
}
|
|
|
|
OS << FH;
|
|
OS << F;
|
|
|
|
if (EType == EmitterType::Compress)
|
|
OS << "\n#endif //GEN_COMPRESS_INSTR\n";
|
|
else if (EType == EmitterType::Uncompress)
|
|
OS << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
|
|
else if (EType == EmitterType::CheckCompress)
|
|
OS << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n";
|
|
}
|
|
|
|
void CompressInstEmitter::run(raw_ostream &OS) {
|
|
// Process the CompressPat definitions, validating them as we do so.
|
|
for (const Record *Pat : Records.getAllDerivedDefinitions("CompressPat"))
|
|
evaluateCompressPat(Pat);
|
|
|
|
// Emit file header.
|
|
emitSourceFileHeader("Compress instruction Source Fragment", OS, Records);
|
|
// Generate compressInst() function.
|
|
emitCompressInstEmitter(OS, EmitterType::Compress);
|
|
// Generate uncompressInst() function.
|
|
emitCompressInstEmitter(OS, EmitterType::Uncompress);
|
|
// Generate isCompressibleInst() function.
|
|
emitCompressInstEmitter(OS, EmitterType::CheckCompress);
|
|
}
|
|
|
|
static TableGen::Emitter::OptClass<CompressInstEmitter>
|
|
X("gen-compress-inst-emitter", "Generate compressed instructions.");
|