3bffb1cd0e
Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469
20 lines
1.1 KiB
LLVM
20 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-after=si-insert-skips < %s | FileCheck --check-prefix=GCN %s
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; GCN-LABEL: name: syncscopes
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; GCN: FLAT_STORE_DWORD killed renamable $vgpr1_vgpr2, killed renamable $vgpr0, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("agent") seq_cst 4 into %ir.agent_out)
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; GCN: FLAT_STORE_DWORD killed renamable $vgpr4_vgpr5, killed renamable $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
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; GCN: FLAT_STORE_DWORD killed renamable $vgpr7_vgpr8, killed renamable $vgpr6, 0, 0, implicit $exec, implicit $flat_scr :: (store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
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define void @syncscopes(
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i32 %agent,
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i32* %agent_out,
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i32 %workgroup,
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i32* %workgroup_out,
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i32 %wavefront,
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i32* %wavefront_out) {
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entry:
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store atomic i32 %agent, i32* %agent_out syncscope("agent") seq_cst, align 4
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store atomic i32 %workgroup, i32* %workgroup_out syncscope("workgroup") seq_cst, align 4
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store atomic i32 %wavefront, i32* %wavefront_out syncscope("wavefront") seq_cst, align 4
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ret void
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}
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