cfebd77742
One of the exit criteria of computeKnownBits is whether we reach the max
recursive call depth. Before this patch we would check that the
depth is exactly equal to max depth to exit.
Depth may get bigger than max depth if it gets passed to a different
GISelKnownBits object.
This may happen when say a generic part uses a GISelKnownBits object
with some max depth, but then we hit TL.computeKnownBitsForTargetInstr
which creates a new GISelKnownBits object with a different and smaller
depth. In that situation, when we hit the max depth check for the first
time in the target specific GISelKnownBits object, depth may already
be bigger than the current max depth. Hence we would continue to compute
the known bits, until we ran through the full depth of the chain of
computation or ran out of stack space.
For instance, let say we have
GISelKnownBits Info(/*MaxDepth*/ = 10);
Info.getKnownBits(Foo)
// 9 recursive calls to computeKnownBitsImpl.
// Then we hit a target specific instruction.
// The target specific GISelKnownBits does this:
GISelKnownBits TargetSpecificInfo(/*MaxDepth*/ = 6)
TargetSpecificInfo.computeKnownBitsImpl() // <-- next max depth checks would
// always return false.
This commit does not have any test case, none of the in-tree targets
use computeKnownBitsForTargetInstr.
461 lines
17 KiB
C++
461 lines
17 KiB
C++
//===- lib/CodeGen/GlobalISel/GISelKnownBits.cpp --------------*- C++ *-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// Provides analysis for querying information about KnownBits during GISel
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/// passes.
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//
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//===------------------
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#define DEBUG_TYPE "gisel-known-bits"
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using namespace llvm;
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char llvm::GISelKnownBitsAnalysis::ID = 0;
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INITIALIZE_PASS(GISelKnownBitsAnalysis, DEBUG_TYPE,
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"Analysis for ComputingKnownBits", false, true)
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GISelKnownBits::GISelKnownBits(MachineFunction &MF, unsigned MaxDepth)
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: MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),
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DL(MF.getFunction().getParent()->getDataLayout()), MaxDepth(MaxDepth) {}
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Align GISelKnownBits::inferAlignmentForFrameIdx(int FrameIdx, int Offset,
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const MachineFunction &MF) {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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return commonAlignment(Align(MFI.getObjectAlignment(FrameIdx)), Offset);
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// TODO: How to handle cases with Base + Offset?
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}
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MaybeAlign GISelKnownBits::inferPtrAlignment(const MachineInstr &MI) {
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if (MI.getOpcode() == TargetOpcode::G_FRAME_INDEX) {
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int FrameIdx = MI.getOperand(1).getIndex();
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return inferAlignmentForFrameIdx(FrameIdx, 0, *MI.getMF());
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}
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return None;
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}
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void GISelKnownBits::computeKnownBitsForFrameIndex(Register R, KnownBits &Known,
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const APInt &DemandedElts,
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unsigned Depth) {
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const MachineInstr &MI = *MRI.getVRegDef(R);
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computeKnownBitsForAlignment(Known, inferPtrAlignment(MI));
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}
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void GISelKnownBits::computeKnownBitsForAlignment(KnownBits &Known,
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MaybeAlign Alignment) {
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if (Alignment)
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// The low bits are known zero if the pointer is aligned.
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Known.Zero.setLowBits(Log2(Alignment));
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}
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KnownBits GISelKnownBits::getKnownBits(MachineInstr &MI) {
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return getKnownBits(MI.getOperand(0).getReg());
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}
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KnownBits GISelKnownBits::getKnownBits(Register R) {
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KnownBits Known;
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LLT Ty = MRI.getType(R);
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APInt DemandedElts =
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Ty.isVector() ? APInt::getAllOnesValue(Ty.getNumElements()) : APInt(1, 1);
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computeKnownBitsImpl(R, Known, DemandedElts);
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return Known;
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}
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bool GISelKnownBits::signBitIsZero(Register R) {
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LLT Ty = MRI.getType(R);
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unsigned BitWidth = Ty.getScalarSizeInBits();
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return maskedValueIsZero(R, APInt::getSignMask(BitWidth));
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}
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APInt GISelKnownBits::getKnownZeroes(Register R) {
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return getKnownBits(R).Zero;
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}
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APInt GISelKnownBits::getKnownOnes(Register R) { return getKnownBits(R).One; }
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void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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const APInt &DemandedElts,
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unsigned Depth) {
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MachineInstr &MI = *MRI.getVRegDef(R);
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unsigned Opcode = MI.getOpcode();
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LLT DstTy = MRI.getType(R);
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// Handle the case where this is called on a register that does not have a
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// type constraint (i.e. it has a register class constraint instead). This is
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// unlikely to occur except by looking through copies but it is possible for
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// the initial register being queried to be in this state.
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if (!DstTy.isValid()) {
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Known = KnownBits();
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return;
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}
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unsigned BitWidth = DstTy.getSizeInBits();
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Known = KnownBits(BitWidth); // Don't know anything
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if (DstTy.isVector())
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return; // TODO: Handle vectors.
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// Depth may get bigger than max depth if it gets passed to a different
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// GISelKnownBits object.
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// This may happen when say a generic part uses a GISelKnownBits object
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// with some max depth, but then we hit TL.computeKnownBitsForTargetInstr
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// which creates a new GISelKnownBits object with a different and smaller
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// depth. If we just check for equality, we would never exit if the depth
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// that is passed down to the target specific GISelKnownBits object is
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// already bigger than its max depth.
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if (Depth >= getMaxDepth())
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return;
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if (!DemandedElts)
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return; // No demanded elts, better to assume we don't know anything.
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KnownBits Known2;
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switch (Opcode) {
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default:
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TL.computeKnownBitsForTargetInstr(*this, R, Known, DemandedElts, MRI,
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Depth);
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break;
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case TargetOpcode::COPY:
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case TargetOpcode::G_PHI:
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case TargetOpcode::PHI: {
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Known.One = APInt::getAllOnesValue(BitWidth);
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Known.Zero = APInt::getAllOnesValue(BitWidth);
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// Destination registers should not have subregisters at this
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// point of the pipeline, otherwise the main live-range will be
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// defined more than once, which is against SSA.
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assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?");
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// PHI's operand are a mix of registers and basic blocks interleaved.
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// We only care about the register ones.
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for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {
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const MachineOperand &Src = MI.getOperand(Idx);
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Register SrcReg = Src.getReg();
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// Look through trivial copies and phis but don't look through trivial
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// copies or phis of the form `%1:(s32) = OP %0:gpr32`, known-bits
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// analysis is currently unable to determine the bit width of a
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// register class.
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//
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// We can't use NoSubRegister by name as it's defined by each target but
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// it's always defined to be 0 by tablegen.
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if (SrcReg.isVirtual() && Src.getSubReg() == 0 /*NoSubRegister*/ &&
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MRI.getType(SrcReg).isValid()) {
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// For COPYs we don't do anything, don't increase the depth.
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computeKnownBitsImpl(SrcReg, Known2, DemandedElts,
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Depth + (Opcode != TargetOpcode::COPY));
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Known.One &= Known2.One;
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Known.Zero &= Known2.Zero;
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} else {
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// We know nothing.
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Known = KnownBits(BitWidth);
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break;
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}
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}
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break;
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}
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case TargetOpcode::G_CONSTANT: {
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auto CstVal = getConstantVRegVal(R, MRI);
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if (!CstVal)
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break;
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Known.One = *CstVal;
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Known.Zero = ~Known.One;
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break;
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}
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case TargetOpcode::G_FRAME_INDEX: {
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computeKnownBitsForFrameIndex(R, Known, DemandedElts);
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break;
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}
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case TargetOpcode::G_SUB: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known = KnownBits::computeForAddSub(/*Add*/ false, /*NSW*/ false, Known,
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Known2);
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break;
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}
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case TargetOpcode::G_XOR: {
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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// Output known-0 bits are known if clear or set in both the LHS & RHS.
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APInt KnownZeroOut = (Known.Zero & Known2.Zero) | (Known.One & Known2.One);
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// Output known-1 are known to be set if set in only one of the LHS, RHS.
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Known.One = (Known.Zero & Known2.One) | (Known.One & Known2.Zero);
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Known.Zero = KnownZeroOut;
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break;
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}
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case TargetOpcode::G_PTR_ADD: {
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// G_PTR_ADD is like G_ADD. FIXME: Is this true for all targets?
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LLT Ty = MRI.getType(MI.getOperand(1).getReg());
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if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
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break;
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LLVM_FALLTHROUGH;
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}
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case TargetOpcode::G_ADD: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
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Depth + 1);
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Known =
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KnownBits::computeForAddSub(/*Add*/ true, /*NSW*/ false, Known, Known2);
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break;
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}
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case TargetOpcode::G_AND: {
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// If either the LHS or the RHS are Zero, the result is zero.
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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// Output known-1 bits are only known if set in both the LHS & RHS.
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Known.One &= Known2.One;
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// Output known-0 are known to be clear if zero in either the LHS | RHS.
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Known.Zero |= Known2.Zero;
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break;
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}
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case TargetOpcode::G_OR: {
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// If either the LHS or the RHS are Zero, the result is zero.
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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// Output known-0 bits are only known if clear in both the LHS & RHS.
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Known.Zero &= Known2.Zero;
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// Output known-1 are known to be set if set in either the LHS | RHS.
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Known.One |= Known2.One;
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break;
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}
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case TargetOpcode::G_MUL: {
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
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Depth + 1);
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
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Depth + 1);
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// If low bits are zero in either operand, output low known-0 bits.
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// Also compute a conservative estimate for high known-0 bits.
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// More trickiness is possible, but this is sufficient for the
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// interesting case of alignment computation.
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unsigned TrailZ =
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Known.countMinTrailingZeros() + Known2.countMinTrailingZeros();
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unsigned LeadZ =
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std::max(Known.countMinLeadingZeros() + Known2.countMinLeadingZeros(),
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BitWidth) -
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BitWidth;
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Known.resetAll();
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Known.Zero.setLowBits(std::min(TrailZ, BitWidth));
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Known.Zero.setHighBits(std::min(LeadZ, BitWidth));
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break;
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}
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case TargetOpcode::G_SELECT: {
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computeKnownBitsImpl(MI.getOperand(3).getReg(), Known, DemandedElts,
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Depth + 1);
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// If we don't know any bits, early out.
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if (Known.isUnknown())
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break;
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computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
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Depth + 1);
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// Only known if known in both the LHS and RHS.
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Known.One &= Known2.One;
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Known.Zero &= Known2.Zero;
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break;
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}
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case TargetOpcode::G_FCMP:
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case TargetOpcode::G_ICMP: {
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if (TL.getBooleanContents(DstTy.isVector(),
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Opcode == TargetOpcode::G_FCMP) ==
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TargetLowering::ZeroOrOneBooleanContent &&
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BitWidth > 1)
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Known.Zero.setBitsFrom(1);
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break;
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}
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case TargetOpcode::G_SEXT: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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// If the sign bit is known to be zero or one, then sext will extend
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// it to the top bits, else it will just zext.
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Known = Known.sext(BitWidth);
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break;
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}
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case TargetOpcode::G_ANYEXT: {
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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Known = Known.zext(BitWidth, true /* ExtendedBitsAreKnownZero */);
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break;
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}
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case TargetOpcode::G_LOAD: {
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if (MI.hasOneMemOperand()) {
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const MachineMemOperand *MMO = *MI.memoperands_begin();
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if (const MDNode *Ranges = MMO->getRanges()) {
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computeKnownBitsFromRangeMetadata(*Ranges, Known);
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}
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}
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break;
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}
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case TargetOpcode::G_ZEXTLOAD: {
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// Everything above the retrieved bits is zero
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if (MI.hasOneMemOperand())
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Known.Zero.setBitsFrom((*MI.memoperands_begin())->getSizeInBits());
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break;
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}
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_SHL: {
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KnownBits RHSKnown;
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computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
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Depth + 1);
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if (!RHSKnown.isConstant()) {
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LLVM_DEBUG(
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MachineInstr *RHSMI = MRI.getVRegDef(MI.getOperand(2).getReg());
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dbgs() << '[' << Depth << "] Shift not known constant: " << *RHSMI);
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break;
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}
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uint64_t Shift = RHSKnown.getConstant().getZExtValue();
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LLVM_DEBUG(dbgs() << '[' << Depth << "] Shift is " << Shift << '\n');
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computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
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Depth + 1);
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switch (Opcode) {
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case TargetOpcode::G_ASHR:
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Known.Zero = Known.Zero.ashr(Shift);
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Known.One = Known.One.ashr(Shift);
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break;
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case TargetOpcode::G_LSHR:
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Known.Zero = Known.Zero.lshr(Shift);
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Known.One = Known.One.lshr(Shift);
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Known.Zero.setBitsFrom(Known.Zero.getBitWidth() - Shift);
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break;
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case TargetOpcode::G_SHL:
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Known.Zero = Known.Zero.shl(Shift);
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Known.One = Known.One.shl(Shift);
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Known.Zero.setBits(0, Shift);
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break;
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}
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break;
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}
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case TargetOpcode::G_INTTOPTR:
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case TargetOpcode::G_PTRTOINT:
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// Fall through and handle them the same as zext/trunc.
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_ZEXT:
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case TargetOpcode::G_TRUNC: {
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Register SrcReg = MI.getOperand(1).getReg();
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LLT SrcTy = MRI.getType(SrcReg);
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unsigned SrcBitWidth = SrcTy.isPointer()
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? DL.getIndexSizeInBits(SrcTy.getAddressSpace())
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: SrcTy.getSizeInBits();
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assert(SrcBitWidth && "SrcBitWidth can't be zero");
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Known = Known.zextOrTrunc(SrcBitWidth, true);
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computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
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Known = Known.zextOrTrunc(BitWidth, true);
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if (BitWidth > SrcBitWidth)
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Known.Zero.setBitsFrom(SrcBitWidth);
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break;
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}
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}
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assert(!Known.hasConflict() && "Bits known to be one AND zero?");
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LLVM_DEBUG(dbgs() << "[" << Depth << "] Compute known bits: " << MI << "["
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<< Depth << "] Computed for: " << MI << "[" << Depth
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<< "] Known: 0x"
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<< (Known.Zero | Known.One).toString(16, false) << "\n"
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<< "[" << Depth << "] Zero: 0x"
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<< Known.Zero.toString(16, false) << "\n"
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<< "[" << Depth << "] One: 0x"
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<< Known.One.toString(16, false) << "\n");
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}
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unsigned GISelKnownBits::computeNumSignBits(Register R,
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const APInt &DemandedElts,
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unsigned Depth) {
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MachineInstr &MI = *MRI.getVRegDef(R);
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unsigned Opcode = MI.getOpcode();
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if (Opcode == TargetOpcode::G_CONSTANT)
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return MI.getOperand(1).getCImm()->getValue().getNumSignBits();
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if (Depth == getMaxDepth())
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return 1;
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if (!DemandedElts)
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return 1; // No demanded elts, better to assume we don't know anything.
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LLT DstTy = MRI.getType(R);
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// Handle the case where this is called on a register that does not have a
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// type constraint. This is unlikely to occur except by looking through copies
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// but it is possible for the initial register being queried to be in this
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// state.
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if (!DstTy.isValid())
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return 1;
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switch (Opcode) {
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case TargetOpcode::COPY: {
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MachineOperand &Src = MI.getOperand(1);
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if (Src.getReg().isVirtual() && Src.getSubReg() == 0 &&
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MRI.getType(Src.getReg()).isValid()) {
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// Don't increment Depth for this one since we didn't do any work.
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return computeNumSignBits(Src.getReg(), DemandedElts, Depth);
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}
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return 1;
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}
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case TargetOpcode::G_SEXT: {
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Register Src = MI.getOperand(1).getReg();
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LLT SrcTy = MRI.getType(Src);
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unsigned Tmp = DstTy.getScalarSizeInBits() - SrcTy.getScalarSizeInBits();
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return computeNumSignBits(Src, DemandedElts, Depth + 1) + Tmp;
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}
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case TargetOpcode::G_TRUNC: {
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Register Src = MI.getOperand(1).getReg();
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LLT SrcTy = MRI.getType(Src);
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// Check if the sign bits of source go down as far as the truncated value.
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unsigned DstTyBits = DstTy.getScalarSizeInBits();
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unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
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unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1);
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if (NumSrcSignBits > (NumSrcBits - DstTyBits))
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return NumSrcSignBits - (NumSrcBits - DstTyBits);
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break;
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|
}
|
|
default:
|
|
break;
|
|
}
|
|
|
|
// TODO: Handle target instructions
|
|
// TODO: Fall back to known bits
|
|
return 1;
|
|
}
|
|
|
|
unsigned GISelKnownBits::computeNumSignBits(Register R, unsigned Depth) {
|
|
LLT Ty = MRI.getType(R);
|
|
APInt DemandedElts = Ty.isVector()
|
|
? APInt::getAllOnesValue(Ty.getNumElements())
|
|
: APInt(1, 1);
|
|
return computeNumSignBits(R, DemandedElts, Depth);
|
|
}
|
|
|
|
void GISelKnownBitsAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesAll();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
bool GISelKnownBitsAnalysis::runOnMachineFunction(MachineFunction &MF) {
|
|
return false;
|
|
}
|