Craig Topper 35625464c6 [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2 ...

We seem to be inheriting the cost from sse4.1. But if we have 256-bit registers we should be able to do this with just one extract to split the 16i16 and two v8i16->v8i32 operations so our cost should be 3 not 4.

Differential Revision: https://reviews.llvm.org/D73646

2020-01-29 15:52:10 -08:00

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AArch64

[CostModel] Model all extractvalues as free.

2019-08-29 11:50:30 +00:00

AMDGPU

[AMDGPU] Implemented fma cost analysis

2019-12-18 23:54:20 -08:00

ARM

[ARM] Basic gather scatter cost model

2020-01-22 14:41:38 +00:00

PowerPC

[PowerPC] Separate Features that are known to be Power9 specific from Future CPU

2019-11-27 15:40:13 -06:00

RISCV

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00

SystemZ

Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351

2019-12-24 15:57:33 -08:00

X86

[X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2

2020-01-29 15:52:10 -08:00

no_info.ll

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