b777e551f0
Summary: Mem op clustering adds a weak edge in the DAG between two loads or stores that should be clustered, but the direction of this edge is pretty arbitrary (it depends on the sort order of MemOpInfo, which represents the operands of a load or store). This often means that two loads or stores will get reordered even if they would naturally have been scheduled together anyway, which leads to test case churn and goes against the scheduler's "do no harm" philosophy. The fix makes sure that the direction of the edge always matches the original code order of the instructions. Reviewers: atrick, MatzeB, arsenm, rampitec, t.p.northover Subscribers: jvesely, wdng, nhaehnle, kristof.beyls, hiraditya, javed.absar, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72706
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; RUN: llc -mtriple amdgcn-amd-- -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Before the fix that this test was committed with, this code would leave
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; an unused stack slot, causing ScratchSize to be non-zero.
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; GCN-LABEL: store_v3i32:
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; GCN: ds_read_b32
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; GCN: ds_read_b64
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; GCN: ds_write_b32
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; GCN: ds_write_b64
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; GCN: ScratchSize: 0
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define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> %a) nounwind {
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%val = load <3 x i32>, <3 x i32> addrspace(3)* %out
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%val.1 = add <3 x i32> %a, %val
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store <3 x i32> %val.1, <3 x i32> addrspace(3)* %out, align 16
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ret void
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}
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; GCN-LABEL: store_v5i32:
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; GCN: ds_read_b32
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; GCN: ds_read2_b64
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; GCN: ds_write_b32
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; GCN: ds_write2_b64
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; GCN: ScratchSize: 0
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define amdgpu_kernel void @store_v5i32(<5 x i32> addrspace(3)* %out, <5 x i32> %a) nounwind {
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%val = load <5 x i32>, <5 x i32> addrspace(3)* %out
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%val.1 = add <5 x i32> %a, %val
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store <5 x i32> %val.1, <5 x i32> addrspace(3)* %out, align 16
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ret void
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}
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