da0fe5db99
Summary:
This patch introduces the ROLBRd and RORBRd pseudo-instructions,
which implemenent the "traditional" rotate operations; instead of
the AVR rotate instructions that use the carry bit.
The code is not optimized at all. Especially when dealing with
loops of rotate instructions, this codegen should be improved some
day.
Related bug: 41358 <https://bugs.llvm.org/show_bug.cgi?id=41358>
//Note//: This is my first submitted patch.
Reviewers: dylanmckay, Jim
Reviewed By: dylanmckay
Subscribers: hiraditya, llvm-commits, dylanmckay, dsprenkels
Tags: #llvm
Patched by dsprenkels (Daan Sprenkels)
Differential Revision: https://reviews.llvm.org/D60365
60 lines
1.0 KiB
LLVM
60 lines
1.0 KiB
LLVM
; RUN: llc < %s -march=avr | FileCheck %s
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; Bit rotation tests.
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; CHECK-LABEL: rol8:
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define i8 @rol8(i8 %val, i8 %amt) {
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; CHECK: andi r22, 7
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; CHECK-NEXT: cpi r22, 0
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; CHECK-NEXT: breq LBB0_2
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; CHECK-NEXT: LBB0_1:
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: subi r22, 1
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; CHECK-NEXT: brne LBB0_1
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; CHECK-NEXT:LBB0_2:
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; CHECK-NEXT: ret
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%mod = urem i8 %amt, 8
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%inv = sub i8 8, %mod
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%parta = shl i8 %val, %mod
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%partb = lshr i8 %val, %inv
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%rotl = or i8 %parta, %partb
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ret i8 %rotl
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}
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; CHECK-LABEL: ror8:
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define i8 @ror8(i8 %val, i8 %amt) {
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; CHECK: andi r22, 7
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; CHECK-NEXT: cpi r22, 0
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; CHECK-NEXT: breq LBB1_2
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; CHECK-NEXT: LBB1_1:
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; CHECK-NEXT: lsr r24
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; CHECK-NEXT: ldi r0, 0
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; CHECK-NEXT: ror r0
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; CHECK-NEXT: or r24, r0
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; CHECK-NEXT: subi r22, 1
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; CHECK-NEXT: brne LBB1_1
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; CHECK-NEXT:LBB1_2:
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; CHECK-NEXT: ret
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%mod = urem i8 %amt, 8
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%inv = sub i8 8, %mod
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%parta = lshr i8 %val, %mod
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%partb = shl i8 %val, %inv
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%rotr = or i8 %parta, %partb
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ret i8 %rotr
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}
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