6512473cee
This patch aims to improve the code generation for float vector gather on POWER9. Patterns have been implemented to utilize instructions that deliver improved performance. Patch by: Kamau Bridgeman Differential Revision: https://reviews.llvm.org/D62908
49 lines
2.2 KiB
LLVM
49 lines
2.2 KiB
LLVM
; NOTE: This test ensures that for both Big and Little Endian cases a set of
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; NOTE: 4 floats is gathered into a v4f32 register using xxmrghw and xxmrgld
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s -check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s -check-prefix=CHECK-BE
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define dso_local <4 x float> @vector_gatherf(float* nocapture readonly %a,
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float* nocapture readonly %b, float* nocapture readonly %c,
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float* nocapture readonly %d) {
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; C code from which this IR test case was generated:
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; vector float test(float *a, float *b, float *c, float *d) {
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; return (vector float) { *a, *b, *c, *d };
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; }
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; CHECK-LE-LABEL: vector_gatherf:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r6
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; CHECK-LE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r5
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; CHECK-LE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r4
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; CHECK-LE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r3
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; CHECK-LE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]
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; CHECK-LE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]
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; CHECK-LE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]
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; CHECK-LE-NEXT: blr
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; CHECK-BE-LABEL: vector_gatherf:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r3
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; CHECK-BE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r4
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; CHECK-BE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r5
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; CHECK-BE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r6
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; CHECK-BE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]
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; CHECK-BE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]
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; CHECK-BE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load float, float* %a, align 4
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%vecinit = insertelement <4 x float> undef, float %0, i32 0
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%1 = load float, float* %b, align 4
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%vecinit1 = insertelement <4 x float> %vecinit, float %1, i32 1
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%2 = load float, float* %c, align 4
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%vecinit2 = insertelement <4 x float> %vecinit1, float %2, i32 2
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%3 = load float, float* %d, align 4
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%vecinit3 = insertelement <4 x float> %vecinit2, float %3, i32 3
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ret <4 x float> %vecinit3
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}
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