ede8293d7d
The back-end currently has special DAGCombine code to detect cases where two floating-point extend or truncate operations can be combined into a single vector operation. This patch extends that support to also handle strict FP operations. Note that currently only the case where both operations have the same input chain are supported. This already suffices to cover the common case where the operations result from scalarizing a non-legal vector type. More general cases can be supported in the future.
62 lines
2.5 KiB
LLVM
62 lines
2.5 KiB
LLVM
; Test conversions between different-sized float elements.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata)
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declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
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declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(<2 x float>, metadata)
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declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
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; Test cases where both elements of a v2f64 are converted to f32s.
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define void @f1(<2 x double> %val, <2 x float> *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vledb {{%v[0-9]+}}, %v24, 0, 0
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; CHECK: br %r14
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%res = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
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<2 x double> %val,
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metadata !"round.dynamic",
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metadata !"fpexcept.strict") #0
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store <2 x float> %res, <2 x float> *%ptr
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ret void
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}
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; Test conversion of an f64 in a vector register to an f32.
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define float @f2(<2 x double> %vec) #0 {
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; CHECK-LABEL: f2:
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; CHECK: wledb %f0, %v24, 0, 0
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; CHECK: br %r14
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%scalar = extractelement <2 x double> %vec, i32 0
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%ret = call float @llvm.experimental.constrained.fptrunc.f32.f64(
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double %scalar,
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metadata !"round.dynamic",
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metadata !"fpexcept.strict") #0
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ret float %ret
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}
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; Test cases where even elements of a v4f32 are converted to f64s.
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define <2 x double> @f3(<4 x float> %vec) {
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; CHECK-LABEL: f3:
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; CHECK: vldeb %v24, {{%v[0-9]+}}
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; CHECK: br %r14
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%shuffle = shufflevector <4 x float> %vec, <4 x float> undef, <2 x i32> <i32 0, i32 2>
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%res = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
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<2 x float> %shuffle,
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metadata !"fpexcept.strict") #0
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ret <2 x double> %res
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}
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; Test conversion of an f32 in a vector register to an f64.
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define double @f4(<4 x float> %vec) {
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; CHECK-LABEL: f4:
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; CHECK: wldeb %f0, %v24
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; CHECK: br %r14
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%scalar = extractelement <4 x float> %vec, i32 0
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%ret = call double @llvm.experimental.constrained.fpext.f64.f32(
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float %scalar,
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metadata !"fpexcept.strict") #0
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ret double %ret
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}
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attributes #0 = { strictfp }
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