42350cd893
Introduce a method to walk through use-def chains to decide whether it's possible to remove a given instruction and its users. These instructions are then stored in a set until the end of the transform when they're erased. This is now used to perform checks on the iteration count (LoopDec chain), element count (VCTP chain) and the possibly redundant iteration count. As well as being able to remove chains of instructions, we know also check that the sub feeding the vctp is producing the expected value. Differential Revision: https://reviews.llvm.org/D71837
180 lines
8.6 KiB
YAML
180 lines
8.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
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# There are 2 SUBS, so don't use tail predication
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-unknown-eabi"
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define dso_local void @use_before_def(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
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entry:
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%cmp8 = icmp sgt i32 %N, 0
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%0 = add i32 %N, 3
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%1 = lshr i32 %0, 2
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%2 = shl nuw i32 %1, 2
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%3 = add i32 %2, -4
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%4 = lshr i32 %3, 2
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%5 = add nuw nsw i32 %4, 1
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br i1 %cmp8, label %vector.ph, label %for.cond.cleanup
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vector.ph: ; preds = %entry
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call void @llvm.set.loop.iterations.i32(i32 %5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv17 = phi i32* [ %scevgep18, %vector.body ], [ %A, %vector.ph ]
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%lsr.iv14 = phi i32* [ %scevgep15, %vector.body ], [ %C, %vector.ph ]
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%lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %B, %vector.ph ]
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%6 = phi i32 [ %5, %vector.ph ], [ %11, %vector.body ]
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%7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
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%lsr.iv13 = bitcast i32* %lsr.iv to <4 x i32>*
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%lsr.iv1416 = bitcast i32* %lsr.iv14 to <4 x i32>*
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%lsr.iv1719 = bitcast i32* %lsr.iv17 to <4 x i32>*
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%8 = call <4 x i1> @llvm.arm.vctp32(i32 %7)
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%9 = sub i32 %7, 4
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%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)
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%wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)
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%10 = add nsw <4 x i32> %wide.masked.load12, %wide.masked.load
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %10, <4 x i32>* %lsr.iv1719, i32 4, <4 x i1> %8)
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%scevgep = getelementptr i32, i32* %lsr.iv, i32 4
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%scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4
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%scevgep18 = getelementptr i32, i32* %lsr.iv17, i32 4
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%11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
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%12 = icmp ne i32 %11, 0
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br i1 %12, label %vector.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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declare void @llvm.set.loop.iterations.i32(i32)
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declare <4 x i1> @llvm.arm.vctp32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
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...
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---
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name: use_before_def
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: use_before_def
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
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; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
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; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr
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; CHECK: t2IT 11, 8, implicit-def $itstate
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; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
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; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg
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; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
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; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
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; CHECK: $lr = t2DLS killed renamable $lr
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; CHECK: bb.1.vector.body:
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; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
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; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
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; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
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; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
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; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
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; CHECK: bb.2.for.cond.cleanup:
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; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r7 = frame-setup tMOVr $sp, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_register $r7
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tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr
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t2IT 11, 8, implicit-def $itstate
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tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
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renamable $lr = t2MOVi 1, 14, $noreg, $noreg
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renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
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renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
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t2DoLoopStart renamable $lr
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bb.1.vector.body:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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liveins: $lr, $r0, $r1, $r2, $r3
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renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
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MVE_VPST 4, implicit $vpr
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renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
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renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
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renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
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renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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MVE_VPST 8, implicit $vpr
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renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
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t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
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tB %bb.2, 14, $noreg
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bb.2.for.cond.cleanup:
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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