addc27bc43
Summary: In the scope of the lowering phase from GPU to ROCDL, the intructions for the conversion patterns seems to be wrong. According to https://github.com/ROCm-Developer-Tools/HIP/blob/master/include/hip/hcc_detail/math_fwd.h the instructions need two underscores in the beginning instead of one. Reviewers: nicolasvasilache, herhut, rriddle Reviewed By: herhut, rriddle Subscribers: merge_guards_bot, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, csigg, arpith-jacob, mgester, lucyrfox, herhut, liufengdb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73535
85 lines
3.6 KiB
C++
85 lines
3.6 KiB
C++
//===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate ROCDLIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
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#include "mlir/Dialect/GPU/GPUDialect.h"
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#include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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using namespace mlir;
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namespace {
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// A pass that replaces all occurrences of GPU device operations with their
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// corresponding ROCDL equivalent.
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//
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// This pass only handles device code and is not meant to be run on GPU host
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// code.
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class LowerGpuOpsToROCDLOpsPass
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: public OperationPass<LowerGpuOpsToROCDLOpsPass, gpu::GPUModuleOp> {
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public:
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void runOnOperation() override {
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gpu::GPUModuleOp m = getOperation();
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OwningRewritePatternList patterns;
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LLVMTypeConverter converter(m.getContext());
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populateStdToLLVMConversionPatterns(converter, patterns);
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patterns.insert<
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GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp,
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ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp,
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ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>,
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GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp,
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ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>,
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GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp,
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ROCDL::GridDimYOp, ROCDL::GridDimZOp>>(
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converter);
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patterns.insert<OpToFuncCallLowering<AbsFOp>>(converter, "__ocml_fabs_f32",
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"__ocml_fabs_f64");
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patterns.insert<OpToFuncCallLowering<CeilFOp>>(converter, "__ocml_ceil_f32",
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"__ocml_ceil_f64");
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patterns.insert<OpToFuncCallLowering<CosOp>>(converter, "__ocml_cos_f32",
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"__ocml_cos_f64");
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patterns.insert<OpToFuncCallLowering<ExpOp>>(converter, "__ocml_exp_f32",
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"__ocml_exp_f64");
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patterns.insert<OpToFuncCallLowering<TanhOp>>(converter, "__ocml_tanh_f32",
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"__ocml_tanh_f64");
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ConversionTarget target(getContext());
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target.addLegalDialect<LLVM::LLVMDialect, ROCDL::ROCDLDialect>();
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target.addIllegalOp<LLVM::FAbsOp, LLVM::FCeilOp, LLVM::CosOp,
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LLVM::ExpOp>();
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target.addDynamicallyLegalOp<FuncOp>(
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[&](FuncOp op) { return converter.isSignatureLegal(op.getType()); });
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if (failed(applyPartialConversion(m, target, patterns, &converter)))
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signalPassFailure();
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}
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};
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} // anonymous namespace
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std::unique_ptr<OpPassBase<gpu::GPUModuleOp>>
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mlir::createLowerGpuOpsToROCDLOpsPass() {
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return std::make_unique<LowerGpuOpsToROCDLOpsPass>();
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}
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static PassRegistration<LowerGpuOpsToROCDLOpsPass>
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pass("convert-gpu-to-rocdl",
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"Generate ROCDL operations for gpu operations");
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