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413596ee45d327a7254d9f3d5f89bf58bbcbb310
clang-p2996/llvm/lib/Target/RISCV
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Craig Topper 413596ee45 [RISCV] Teach debug output from assembly parser to print register names instead of enum values.
2020-12-14 17:22:55 -08:00
..
AsmParser
[RISCV] Teach debug output from assembly parser to print register names instead of enum values.
2020-12-14 17:22:55 -08:00
Disassembler
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
MCTargetDesc
[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output
2020-12-14 10:50:26 -08:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output
2020-12-14 10:50:26 -08:00
CMakeLists.txt
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCV.h
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCV.td
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
2020-12-10 19:25:51 +00:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCleanupVSETVLI.cpp
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
2020-12-04 11:39:30 -08:00
RISCVFrameLowering.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVInstrFormats.td
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVInstrInfo.cpp
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
2020-12-04 10:34:12 -08:00
RISCVInstrInfo.h
[RISCV] Don't include CodeGen layer files in MC layer
2020-11-12 07:45:38 -08:00
RISCVInstrInfo.td
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
2020-12-10 19:25:51 +00:00
RISCVInstrInfoA.td
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RISCVInstrInfoB.td
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
2020-12-10 19:25:51 +00:00
RISCVInstrInfoC.td
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
2020-12-04 10:34:12 -08:00
RISCVInstrInfoD.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td
[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.
2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
2020-12-04 11:39:30 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Separate masked and unmasked definitions for pseudo instructions.
2020-12-11 14:02:56 +08:00
RISCVInstrInfoZfh.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp
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RISCVISelDAGToDAG.cpp
[RISCV] Use SDLoc created early in RISCVDAGToDAGISel::Select instead of recreating it in multiple cases in the switch. NFC
2020-12-08 21:13:25 -08:00
RISCVISelDAGToDAG.h
[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
2020-11-20 10:25:47 -08:00
RISCVISelLowering.cpp
[RISCV] Use tail agnostic policy for vsetvli instruction emitted in the custom inserter
2020-12-10 19:48:03 -08:00
RISCVISelLowering.h
[RISCV] Merge FMV_H_X_RV32/FMV_H_X_RV64 into a single opcode. Same with FMV_X_ANYEXTH_RV32/RV64
2020-12-03 11:12:40 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
[RISCV] Separate masked and unmasked definitions for pseudo instructions.
2020-12-11 14:02:56 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
2020-12-04 11:39:30 -08:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Initial infrastructure for code generation of the RISC-V V-extension
2020-12-04 11:39:30 -08:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSubtarget.h
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVSystemOperands.td
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RISCVTargetMachine.cpp
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00