4154ada1d4
Implement Xtensa FP Option instructions and lowering of the base FP operations with tests. Implement UR registers parsing. Fix loading from constant pool callee, basic block, globaladdress and jumptable addresses. Also fixed potential memory leakage when several similar XtensaConstantPoolValue objects are created Fix lowering i32 immediate.
520 lines
20 KiB
C++
520 lines
20 KiB
C++
//===-- XtensaDisassembler.cpp - Disassembler for Xtensa ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the XtensaDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/XtensaMCTargetDesc.h"
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#include "TargetInfo/XtensaTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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#define DEBUG_TYPE "Xtensa-disassembler"
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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class XtensaDisassembler : public MCDisassembler {
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bool IsLittleEndian;
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public:
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XtensaDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool isLE)
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: MCDisassembler(STI, Ctx), IsLittleEndian(isLE) {}
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bool hasDensity() const { return STI.hasFeature(Xtensa::FeatureDensity); }
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createXtensaDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new XtensaDisassembler(STI, Ctx, true);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler() {
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TargetRegistry::RegisterMCDisassembler(getTheXtensaTarget(),
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createXtensaDisassembler);
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}
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const MCPhysReg ARDecoderTable[] = {
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Xtensa::A0, Xtensa::SP, Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5,
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Xtensa::A6, Xtensa::A7, Xtensa::A8, Xtensa::A9, Xtensa::A10, Xtensa::A11,
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Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15};
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static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= std::size(ARDecoderTable))
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return MCDisassembler::Fail;
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MCPhysReg Reg = ARDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 3)
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return MCDisassembler::Fail;
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MCPhysReg Reg = Xtensa::M0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMR01RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 1)
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return MCDisassembler::Fail;
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MCPhysReg Reg = Xtensa::M0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 1)
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return MCDisassembler::Fail;
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MCPhysReg Reg = Xtensa::M2 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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MCPhysReg Reg = Xtensa::F0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeURRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 255)
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return MCDisassembler::Fail;
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Xtensa::RegisterAccessType RAType = Inst.getOpcode() == Xtensa::WUR
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? Xtensa::REGISTER_WRITE
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: Xtensa::REGISTER_READ;
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const XtensaDisassembler *Dis =
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static_cast<const XtensaDisassembler *>(Decoder);
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const MCRegisterInfo *MRI = Dis->getContext().getRegisterInfo();
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MCPhysReg Reg = Xtensa::getUserRegister(RegNo, *MRI);
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if (!Xtensa::checkRegister(Reg, Decoder->getSubtargetInfo().getFeatureBits(),
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RAType))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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struct DecodeRegister {
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MCPhysReg Reg;
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uint32_t RegNo;
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};
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const DecodeRegister SRDecoderTable[] = {
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{Xtensa::LBEG, 0}, {Xtensa::LEND, 1},
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{Xtensa::LCOUNT, 2}, {Xtensa::SAR, 3},
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{Xtensa::BREG, 4}, {Xtensa::LITBASE, 5},
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{Xtensa::ACCLO, 16}, {Xtensa::ACCHI, 17},
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{Xtensa::M0, 32}, {Xtensa::M1, 33},
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{Xtensa::M2, 34}, {Xtensa::M3, 35},
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{Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73},
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{Xtensa::IBREAKENABLE, 96}, {Xtensa::MEMCTL, 97},
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{Xtensa::DDR, 104}, {Xtensa::IBREAKA0, 128},
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{Xtensa::IBREAKA1, 129}, {Xtensa::DBREAKA0, 144},
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{Xtensa::DBREAKA1, 145}, {Xtensa::DBREAKC0, 160},
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{Xtensa::DBREAKC1, 161}, {Xtensa::CONFIGID0, 176},
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{Xtensa::EPC1, 177}, {Xtensa::EPC2, 178},
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{Xtensa::EPC3, 179}, {Xtensa::EPC4, 180},
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{Xtensa::EPC5, 181}, {Xtensa::EPC6, 182},
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{Xtensa::EPC7, 183}, {Xtensa::DEPC, 192},
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{Xtensa::EPS2, 194}, {Xtensa::EPS3, 195},
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{Xtensa::EPS4, 196}, {Xtensa::EPS5, 197},
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{Xtensa::EPS6, 198}, {Xtensa::EPS7, 199},
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{Xtensa::CONFIGID1, 208}, {Xtensa::EXCSAVE1, 209},
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{Xtensa::EXCSAVE2, 210}, {Xtensa::EXCSAVE3, 211},
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{Xtensa::EXCSAVE4, 212}, {Xtensa::EXCSAVE5, 213},
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{Xtensa::EXCSAVE6, 214}, {Xtensa::EXCSAVE7, 215},
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{Xtensa::CPENABLE, 224}, {Xtensa::INTERRUPT, 226},
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{Xtensa::INTCLEAR, 227}, {Xtensa::INTENABLE, 228},
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{Xtensa::PS, 230}, {Xtensa::VECBASE, 231},
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{Xtensa::EXCCAUSE, 232}, {Xtensa::DEBUGCAUSE, 233},
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{Xtensa::CCOUNT, 234}, {Xtensa::PRID, 235},
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{Xtensa::ICOUNT, 236}, {Xtensa::ICOUNTLEVEL, 237},
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{Xtensa::EXCVADDR, 238}, {Xtensa::CCOMPARE0, 240},
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{Xtensa::CCOMPARE1, 241}, {Xtensa::CCOMPARE2, 242},
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{Xtensa::MISC0, 244}, {Xtensa::MISC1, 245},
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{Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
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static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 255)
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return MCDisassembler::Fail;
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Xtensa::RegisterAccessType RAType =
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Inst.getOpcode() == Xtensa::WSR
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? Xtensa::REGISTER_WRITE
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: (Inst.getOpcode() == Xtensa::RSR ? Xtensa::REGISTER_READ
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: Xtensa::REGISTER_EXCHANGE);
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for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {
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if (SRDecoderTable[i].RegNo == RegNo) {
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MCPhysReg Reg = SRDecoderTable[i].Reg;
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// Handle special case. The INTERRUPT/INTSET registers use the same
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// encoding, but INTERRUPT used for read and INTSET for write.
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if (Reg == Xtensa::INTERRUPT && RAType == Xtensa::REGISTER_WRITE) {
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Reg = Xtensa::INTSET;
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}
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if (!Xtensa::checkRegister(
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Reg, Decoder->getSubtargetInfo().getFeatureBits(), RAType))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeBRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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MCPhysReg Reg = Xtensa::B0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t InstSize, MCInst &MI,
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const void *Decoder) {
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const MCDisassembler *Dis = static_cast<const MCDisassembler *>(Decoder);
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return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
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/*OpSize=*/0, InstSize);
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}
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static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<18>(Imm) && "Invalid immediate");
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Inst.addOperand(
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MCOperand::createImm(SignExtend64<20>(Imm << 2) + (Address & 0x3)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<18>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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switch (Inst.getOpcode()) {
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case Xtensa::BEQZ:
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case Xtensa::BGEZ:
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case Xtensa::BLTZ:
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case Xtensa::BNEZ:
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assert(isUInt<12>(Imm) && "Invalid immediate");
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if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true,
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Address, 0, 3, Inst, Decoder))
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Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
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break;
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default:
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assert(isUInt<8>(Imm) && "Invalid immediate");
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if (!tryAddingSymbolicOperand(SignExtend64<8>(Imm) + 4 + Address, true,
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Address, 0, 3, Inst, Decoder))
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Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeLoopOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<8>(Imm) && "Invalid immediate");
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if (!tryAddingSymbolicOperand(Imm + 4 + Address, true, Address, 0, 3, Inst,
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Decoder))
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<16>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(
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SignExtend64<17>((Imm << 2) + 0x40000 + (Address & 0x3))));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<8>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<8>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 8)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm12Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeUimm4Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeUimm5Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<5>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm + 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm1n_15Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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if (!Imm)
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Inst.addOperand(MCOperand::createImm(-1));
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else
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<7>(Imm) && "Invalid immediate");
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if ((Imm & 0x60) == 0x60)
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Inst.addOperand(MCOperand::createImm((~0x1f) | Imm));
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else
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm > 7 ? Imm - 16 : Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<6>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<15>(Imm) && ((Imm & 0x7) == 0) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<5>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(32 - Imm));
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return MCDisassembler::Success;
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}
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static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7,
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8, 10, 12, 16, 32, 64, 128, 256};
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static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(TableB4const[Imm]));
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return MCDisassembler::Success;
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}
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static int64_t TableB4constu[16] = {32768, 65536, 2, 3, 4, 5, 6, 7,
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8, 10, 12, 16, 32, 64, 128, 256};
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static DecodeStatus decodeB4constuOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(TableB4constu[Imm]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm + 7));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
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Inst.addOperand(MCOperand::createImm((Imm >> 4) & 0xff));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMem16Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
|
|
Inst.addOperand(MCOperand::createImm((Imm >> 3) & 0x1fe));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm,
|
|
int64_t Address, const void *Decoder) {
|
|
assert(isUInt<12>(Imm) && "Invalid immediate");
|
|
DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
|
|
Inst.addOperand(MCOperand::createImm((Imm >> 2) & 0x3fc));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeMem32nOperand(MCInst &Inst, uint64_t Imm,
|
|
int64_t Address, const void *Decoder) {
|
|
assert(isUInt<8>(Imm) && "Invalid immediate");
|
|
DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
|
|
Inst.addOperand(MCOperand::createImm((Imm >> 2) & 0x3c));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
/// Read two bytes from the ArrayRef and return 16 bit data sorted
|
|
/// according to the given endianness.
|
|
static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
|
|
uint64_t &Size, uint64_t &Insn,
|
|
bool IsLittleEndian) {
|
|
// We want to read exactly 2 Bytes of data.
|
|
if (Bytes.size() < 2) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (!IsLittleEndian) {
|
|
report_fatal_error("Big-endian mode currently is not supported!");
|
|
} else {
|
|
Insn = (Bytes[1] << 8) | Bytes[0];
|
|
}
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
/// Read three bytes from the ArrayRef and return 24 bit data
|
|
static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
|
|
uint64_t &Size, uint64_t &Insn,
|
|
bool IsLittleEndian) {
|
|
// We want to read exactly 3 Bytes of data.
|
|
if (Bytes.size() < 3) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (!IsLittleEndian) {
|
|
report_fatal_error("Big-endian mode currently is not supported!");
|
|
} else {
|
|
Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
|
|
}
|
|
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
#include "XtensaGenDisassemblerTables.inc"
|
|
|
|
DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
uint64_t Insn;
|
|
DecodeStatus Result;
|
|
|
|
// Parse 16-bit instructions
|
|
if (hasDensity()) {
|
|
Result = readInstruction16(Bytes, Address, Size, Insn, IsLittleEndian);
|
|
if (Result == MCDisassembler::Fail)
|
|
return MCDisassembler::Fail;
|
|
LLVM_DEBUG(dbgs() << "Trying Xtensa 16-bit instruction table :\n");
|
|
Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 2;
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
// Parse Core 24-bit instructions
|
|
Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian);
|
|
if (Result == MCDisassembler::Fail)
|
|
return MCDisassembler::Fail;
|
|
LLVM_DEBUG(dbgs() << "Trying Xtensa 24-bit instruction table :\n");
|
|
Result = decodeInstruction(DecoderTable24, MI, Insn, Address, this, STI);
|
|
if (Result != MCDisassembler::Fail) {
|
|
Size = 3;
|
|
return Result;
|
|
}
|
|
return Result;
|
|
}
|