bed9efed71
MCSymbolizer::tryAddingSymbolicOperand() overloaded the Size parameter to specify either the instruction size or the operand size depending on the architecture. However, for proper symbolic disassembly on X86, we need to know both sizes, as an instruction can have two operands, and the instruction size cannot be reliably calculated based on the operand offset and its size. Hence, split Size into OpSize and InstSize. For X86, the new interface allows to fix a couple of issues: * Correctly adjust the value of PC-relative operands. * Set operand size to zero when the operand is specified implicitly. Differential Revision: https://reviews.llvm.org/D126101
236 lines
8.7 KiB
C++
236 lines
8.7 KiB
C++
//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains declaration for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/DataExtractor.h"
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#include <memory>
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namespace llvm {
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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class Twine;
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//===----------------------------------------------------------------------===//
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// AMDGPUDisassembler
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//===----------------------------------------------------------------------===//
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class AMDGPUDisassembler : public MCDisassembler {
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private:
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std::unique_ptr<MCInstrInfo const> const MCII;
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const MCRegisterInfo &MRI;
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const unsigned TargetMaxInstBytes;
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mutable ArrayRef<uint8_t> Bytes;
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mutable uint32_t Literal;
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mutable bool HasLiteral;
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public:
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AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII);
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~AMDGPUDisassembler() override = default;
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CS) const override;
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const char* getRegClassName(unsigned RegClassID) const;
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MCOperand createRegOperand(unsigned int RegId) const;
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MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
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MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
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template <typename InsnType>
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DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
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uint64_t Address) const {
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assert(MI.getOpcode() == 0);
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assert(MI.getNumOperands() == 0);
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MCInst TmpInst;
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HasLiteral = false;
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const auto SavedBytes = Bytes;
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if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
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MI = TmpInst;
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return MCDisassembler::Success;
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}
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Bytes = SavedBytes;
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return MCDisassembler::Fail;
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}
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Optional<DecodeStatus> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &CStream) const override;
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DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef<uint8_t> Bytes,
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uint64_t KdAddress) const;
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DecodeStatus
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decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor,
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ArrayRef<uint8_t> Bytes,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC1.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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/// Decode as directives that handle COMPUTE_PGM_RSRC2.
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/// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
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/// \param KdStream - Stream to write the disassembled directives to.
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// NOLINTNEXTLINE(readability-identifier-naming)
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DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
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raw_string_ostream &KdStream) const;
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DecodeStatus convertEXPInst(MCInst &MI) const;
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DecodeStatus convertVINTERPInst(MCInst &MI) const;
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DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
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DecodeStatus convertSDWAInst(MCInst &MI) const;
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DecodeStatus convertDPP8Inst(MCInst &MI) const;
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DecodeStatus convertMIMGInst(MCInst &MI) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
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MCOperand decodeOperand_VS_32(unsigned Val) const;
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MCOperand decodeOperand_VS_64(unsigned Val) const;
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MCOperand decodeOperand_VS_128(unsigned Val) const;
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MCOperand decodeOperand_VSrc16(unsigned Val) const;
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MCOperand decodeOperand_VSrcV216(unsigned Val) const;
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MCOperand decodeOperand_VSrcV232(unsigned Val) const;
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MCOperand decodeOperand_VReg_64(unsigned Val) const;
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MCOperand decodeOperand_VReg_96(unsigned Val) const;
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MCOperand decodeOperand_VReg_128(unsigned Val) const;
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MCOperand decodeOperand_VReg_256(unsigned Val) const;
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MCOperand decodeOperand_VReg_512(unsigned Val) const;
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MCOperand decodeOperand_VReg_1024(unsigned Val) const;
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
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MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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MCOperand decodeOperand_SReg_256(unsigned Val) const;
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MCOperand decodeOperand_SReg_512(unsigned Val) const;
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MCOperand decodeOperand_AGPR_32(unsigned Val) const;
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MCOperand decodeOperand_AReg_64(unsigned Val) const;
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MCOperand decodeOperand_AReg_128(unsigned Val) const;
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MCOperand decodeOperand_AReg_256(unsigned Val) const;
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MCOperand decodeOperand_AReg_512(unsigned Val) const;
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MCOperand decodeOperand_AReg_1024(unsigned Val) const;
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MCOperand decodeOperand_AV_32(unsigned Val) const;
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MCOperand decodeOperand_AV_64(unsigned Val) const;
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MCOperand decodeOperand_AV_128(unsigned Val) const;
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MCOperand decodeOperand_AVDst_128(unsigned Val) const;
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MCOperand decodeOperand_AVDst_512(unsigned Val) const;
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enum OpWidthTy {
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OPW32,
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OPW64,
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OPW96,
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OPW128,
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OPW160,
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OPW256,
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OPW512,
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OPW1024,
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OPW16,
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OPWV216,
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OPWV232,
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OPW_LAST_,
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OPW_FIRST_ = OPW32
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};
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unsigned getVgprClassId(const OpWidthTy Width) const;
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unsigned getAgprClassId(const OpWidthTy Width) const;
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unsigned getSgprClassId(const OpWidthTy Width) const;
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unsigned getTtmpClassId(const OpWidthTy Width) const;
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static MCOperand decodeIntImmed(unsigned Imm);
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static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
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MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
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MCOperand decodeLiteralConstant() const;
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MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
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bool MandatoryLiteral = false) const;
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MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSpecialReg32(unsigned Val) const;
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MCOperand decodeSpecialReg64(unsigned Val) const;
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MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
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MCOperand decodeSDWASrc16(unsigned Val) const;
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MCOperand decodeSDWASrc32(unsigned Val) const;
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MCOperand decodeSDWAVopcDst(unsigned Val) const;
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MCOperand decodeBoolReg(unsigned Val) const;
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int getTTmpIdx(unsigned Val) const;
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const MCInstrInfo *getMCII() const { return MCII.get(); }
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bool isVI() const;
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bool isGFX9() const;
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bool isGFX90A() const;
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bool isGFX9Plus() const;
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bool isGFX10() const;
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bool isGFX10Plus() const;
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bool isGFX11() const;
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bool isGFX11Plus() const;
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bool hasArchitectedFlatScratch() const;
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};
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//===----------------------------------------------------------------------===//
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// AMDGPUSymbolizer
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//===----------------------------------------------------------------------===//
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class AMDGPUSymbolizer : public MCSymbolizer {
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private:
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void *DisInfo;
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std::vector<uint64_t> ReferencedAddresses;
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public:
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AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
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void *disInfo)
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: MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
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bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
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int64_t Value, uint64_t Address, bool IsBranch,
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uint64_t Offset, uint64_t OpSize,
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uint64_t InstSize) override;
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void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
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int64_t Value,
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uint64_t Address) override;
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ArrayRef<uint64_t> getReferencedAddresses() const override {
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return ReferencedAddresses;
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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