a1c6743922
This patch constructs codegen infra and successfully generate the first 'add' instruction. Add integer calling convention for fixed arguments which are passed with general-purpose registers. New test added here: CodeGen/LoongArch/ir-instruction/add.ll The test file is placed in a subdirectory because we will use subdirctories to distinguish different categories of tests (e.g. intrinsic, inline-asm ...) Reviewed By: MaskRay, SixWeining Differential Revision: https://reviews.llvm.org/D122366
39 lines
1.4 KiB
C++
39 lines
1.4 KiB
C++
//=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the LoongArch implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchInstrInfo.h"
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#include "LoongArch.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "LoongArchGenInstrInfo.inc"
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LoongArchInstrInfo::LoongArchInstrInfo(LoongArchSubtarget &STI)
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// FIXME: add CFSetup and CFDestroy Inst when we implement function call.
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: LoongArchGenInstrInfo() {}
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void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, MCRegister DstReg,
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MCRegister SrcReg, bool KillSrc) const {
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if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(LoongArch::R0);
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return;
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}
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// TODO: Now, we only support GPR->GPR copies.
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llvm_unreachable("LoongArch didn't implement copyPhysReg");
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}
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