33388ae866
This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.
For now, only add instruction definitions for LoongArch basic integer
operations.
Our initial target is a working MC layer rather than codegen,
so appropriate SelectionDAG patterns will come later.
Differential revision: https://reviews.llvm.org/D115861
67 lines
2.2 KiB
C++
67 lines
2.2 KiB
C++
//=- LoongArchMCInstLower.cpp - Convert LoongArch MachineInstr to an MCInst -=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower LoongArch MachineInstrs to their
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// corresponding MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArch.h"
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#include "LoongArchSubtarget.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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bool llvm::lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp,
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const AsmPrinter &AP) {
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switch (MO.getType()) {
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default:
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report_fatal_error(
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"lowerLoongArchMachineOperandToMCOperand: unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::createReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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// TODO: lower special operands
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_BlockAddress:
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case MachineOperand::MO_ExternalSymbol:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_JumpTableIndex:
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break;
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}
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return true;
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}
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bool llvm::lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI, AsmPrinter &AP) {
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OutMI.setOpcode(MI->getOpcode());
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for (const MachineOperand &MO : MI->operands()) {
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MCOperand MCOp;
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if (lowerLoongArchMachineOperandToMCOperand(MO, MCOp, AP))
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OutMI.addOperand(MCOp);
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}
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return false;
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}
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