153dee34f1
This patch adds one SPIRV analysis pass and extends AsmPrinter. It is essential for minimum SPIR-V output. Also it adds several simplest tests to show that the target basically works. Differential Revision: https://reviews.llvm.org/D116465 Authors: Aleksandr Bezzubikov, Lewis Crawford, Ilia Diachkov, Michal Paszkowski, Andrey Tretyakov, Konrad Trifunovic Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Ilia Diachkov <iliya.diyachkov@intel.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
59 lines
2.0 KiB
C++
59 lines
2.0 KiB
C++
//=- SPIRVMCInstLower.cpp - Convert SPIR-V MachineInstr to MCInst -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower SPIR-V MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVMCInstLower.h"
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#include "SPIRV.h"
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#include "SPIRVModuleAnalysis.h"
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#include "SPIRVUtils.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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using namespace llvm;
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void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI,
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SPIRV::ModuleAnalysisInfo *MAI) const {
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OutMI.setOpcode(MI->getOpcode());
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const MachineFunction *MF = MI->getMF();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_GlobalAddress: {
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Register FuncReg = MAI->getFuncReg(MO.getGlobal()->getGlobalIdentifier());
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assert(FuncReg.isValid() && "Cannot find function Id");
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MCOp = MCOperand::createReg(FuncReg);
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::createReg(MAI->getOrCreateMBBRegister(*MO.getMBB()));
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break;
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case MachineOperand::MO_Register: {
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Register NewReg = MAI->getRegisterAlias(MF, MO.getReg());
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MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg : MO.getReg());
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break;
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}
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_FPImmediate:
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MCOp = MCOperand::createDFPImm(
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MO.getFPImm()->getValueAPF().convertToFloat());
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break;
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}
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OutMI.addOperand(MCOp);
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}
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}
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