18ed279a3a
Tablegen definitions for subtarget features and cpp predicate functions to access the features. New Sub-TargetProcessors and common latencies. Simple changes to MIR codegen tests which pass on gfx11 because they have the same output as previous subtargets or operate on pseudo instructions which are reused from previous subtargets. Contributors: Jay Foad <jay.foad@amd.com> Petar Avramovic <Petar.Avramovic@amd.com> Patch 4/N for upstreaming of AMDGPU gfx11 architecture Depends on D124538 Reviewed By: Petar.Avramovic, foad Differential Revision: https://reviews.llvm.org/D125261
81 lines
2.5 KiB
YAML
81 lines
2.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: lower_term_opcodes
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tracksRegLiveness: false
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body: |
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; CHECK-LABEL: name: lower_term_opcodes
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: $sgpr0 = COPY $sgpr1
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: $sgpr0 = S_MOV_B32 0
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: $sgpr0 = S_MOV_B32 &SYMBOL
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; CHECK: bb.3:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: $sgpr0_sgpr1 = COPY $sgpr2_sgpr3
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; CHECK: bb.4:
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; CHECK: successors: %bb.5(0x80000000)
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; CHECK: $sgpr0_sgpr1 = S_MOV_B64 0
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; CHECK: bb.5:
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; CHECK: successors: %bb.6(0x80000000)
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; CHECK: $sgpr0_sgpr1 = S_MOV_B64 &SYMBOL
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; CHECK: bb.6:
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; CHECK: successors: %bb.7(0x80000000)
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; CHECK: $sgpr0 = S_XOR_B32 $sgpr1, $sgpr2, implicit-def $scc
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; CHECK: bb.7:
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; CHECK: successors: %bb.8(0x80000000)
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; CHECK: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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; CHECK: bb.8:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: $sgpr0 = S_OR_B32 $sgpr1, $sgpr2, implicit-def $scc
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; CHECK: bb.9:
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; CHECK: successors: %bb.10(0x80000000)
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; CHECK: $sgpr0_sgpr1 = S_OR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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; CHECK: bb.10:
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; CHECK: successors: %bb.11(0x80000000)
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; CHECK: $sgpr0 = S_ANDN2_B32 $sgpr1, $sgpr2, implicit-def $scc
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; CHECK: bb.11:
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; CHECK: $sgpr0_sgpr1 = S_ANDN2_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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bb.0:
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$sgpr0 = S_MOV_B32_term $sgpr1
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bb.1:
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$sgpr0 = S_MOV_B32_term 0
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bb.3:
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$sgpr0 = S_MOV_B32_term &SYMBOL
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bb.4:
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$sgpr0_sgpr1 = S_MOV_B64_term $sgpr2_sgpr3
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bb.5:
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$sgpr0_sgpr1 = S_MOV_B64_term 0
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bb.6:
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$sgpr0_sgpr1 = S_MOV_B64_term &SYMBOL
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bb.7:
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$sgpr0 = S_XOR_B32_term $sgpr1, $sgpr2, implicit-def $scc
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bb.8:
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$sgpr0_sgpr1 = S_XOR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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bb.9:
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$sgpr0 = S_OR_B32_term $sgpr1, $sgpr2, implicit-def $scc
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bb.10:
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$sgpr0_sgpr1 = S_OR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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bb.11:
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$sgpr0 = S_ANDN2_B32_term $sgpr1, $sgpr2, implicit-def $scc
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bb.12:
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$sgpr0_sgpr1 = S_ANDN2_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
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...
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