c246b7bd4a
Previously any load (global, local or constant) feeding into a global load or store would be counted as an indirect access. This patch only counts global loads feeding into a global load or store. The rationale is that the latency for global loads is generally much larger than the other kinds. As a side effect this makes it easier to write small kernels test cases that are not counted as having indirect accesses, despite the fact that arguments to the kernel are accessed with an SMEM load. Differential Revision: https://reviews.llvm.org/D122804
105 lines
4.4 KiB
LLVM
105 lines
4.4 KiB
LLVM
; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_membound:
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; GCN: MemoryBound: 1
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; GCN: WaveLimiterHint : 1
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define amdgpu_kernel void @test_membound(<4 x i32> addrspace(1)* nocapture readonly %arg, <4 x i32> addrspace(1)* nocapture %arg1) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = zext i32 %tmp to i64
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%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
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%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
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%tmp6 = add nuw nsw i64 %tmp2, 1
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%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
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%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
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store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
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ret void
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}
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; GCN-LABEL: {{^}}test_large_stride:
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; GCN: MemoryBound: 0
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; GCN: WaveLimiterHint : 1
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define amdgpu_kernel void @test_large_stride(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 4096
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%tmp1 = load i32, i32 addrspace(1)* %tmp, align 4
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%mul1 = mul i32 %tmp1, %tmp1
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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store i32 %mul1, i32 addrspace(1)* %tmp2, align 4
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 8192
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%tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4
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%mul4 = mul i32 %tmp4, %tmp4
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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store i32 %mul4, i32 addrspace(1)* %tmp5, align 4
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%tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 12288
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%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
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%mul7 = mul i32 %tmp7, %tmp7
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%tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
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store i32 %mul7, i32 addrspace(1)* %tmp8, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_indirect:
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; GCN: MemoryBound: 0
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; GCN: WaveLimiterHint : 1
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define amdgpu_kernel void @test_indirect(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
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%tmp3 = bitcast i32 addrspace(1)* %arg to <4 x i32> addrspace(1)*
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%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 4
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%tmp5 = extractelement <4 x i32> %tmp4, i32 0
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%tmp6 = sext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp6
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%tmp8 = load i32, i32 addrspace(1)* %tmp7, align 4
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store i32 %tmp8, i32 addrspace(1)* %arg, align 4
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%tmp9 = extractelement <4 x i32> %tmp4, i32 1
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%tmp10 = sext i32 %tmp9 to i64
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%tmp11 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load i32, i32 addrspace(1)* %tmp11, align 4
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store i32 %tmp12, i32 addrspace(1)* %tmp, align 4
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%tmp13 = extractelement <4 x i32> %tmp4, i32 2
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%tmp14 = sext i32 %tmp13 to i64
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%tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp14
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%tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
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store i32 %tmp16, i32 addrspace(1)* %tmp1, align 4
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%tmp17 = extractelement <4 x i32> %tmp4, i32 3
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%tmp18 = sext i32 %tmp17 to i64
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%tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
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%tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
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store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_indirect_through_phi:
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; GCN: MemoryBound: 0
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; GCN: WaveLimiterHint : 0
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define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
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bb:
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%load = load float, float addrspace(1)* %arg, align 8
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%load.f = bitcast float %load to i32
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%n = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb1
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bb1: ; preds = %bb1, %bb
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%phi = phi i32 [ %load.f, %bb ], [ %and2, %bb1 ]
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%ind = phi i32 [ 0, %bb ], [ %inc2, %bb1 ]
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%and1 = and i32 %phi, %n
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%gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %and1
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store float %load, float addrspace(1)* %gep, align 4
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%inc1 = add nsw i32 %phi, 1310720
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%and2 = and i32 %inc1, %n
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%inc2 = add nuw nsw i32 %ind, 1
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%cmp = icmp eq i32 %inc2, 1024
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br i1 %cmp, label %bb2, label %bb1
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bb2: ; preds = %bb1
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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