341623653d
This is another fold generalized from D111530.
We can find a common source for a rotate operation hidden inside an 'or':
https://alive2.llvm.org/ce/z/9pV8hn
Deciding when this is profitable vs. a funnel-shift is tricky, but this
does not show any regressions: if a target has a rotate but it does not
have a funnel-shift, then try to form the rotate here. That is why we
don't have x86 test diffs for the scalar tests that are duplicated from
AArch64 ( 74a65e3834 ) - shld/shrd are available. That also makes it
difficult to show vector diffs - the only case where I found a diff was
on x86 AVX512 or XOP with i64 elements.
There's an additional check for a legal type to avoid a problem seen
with x86-32 where we form a 64-bit rotate but then it gets split
inefficiently. We might avoid that by adding more rotate folds, but
I didn't check to see what is missing on that path.
This gets most of the motivating patterns for AArch64 / ARM that are in
D111530.
We still need a couple of enhancements to setcc pattern matching with
rotate/funnel-shift to get the rest.
Differential Revision: https://reviews.llvm.org/D120933
159 lines
4.6 KiB
LLVM
159 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
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; Optimize expanded SRL/SHL used as an input of
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; SETCC comparing it with zero by removing rotation.
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;
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; See https://bugs.llvm.org/show_bug.cgi?id=50197
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define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_lt_power_of_2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .LBB0_1: @ %loop
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: adds r0, r0, #1
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; CHECK-NEXT: adc r1, r1, #0
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; CHECK-NEXT: orr r2, r1, r0, lsr #16
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: bne .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %exit
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; CHECK-NEXT: bx lr
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br label %loop
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loop:
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%phi.a = phi i64 [ %a, %0 ], [ %inc, %loop ]
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%inc = add i64 %phi.a, 1
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%cmp = icmp ult i64 %inc, 65536
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br i1 %cmp, label %exit, label %loop
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exit:
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ret i64 %inc
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}
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define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_srl_eq_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r1, r0, lsr #17
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: bx lr
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%srl = lshr i64 %a, 17
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%cmp = icmp eq i64 %srl, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_srl_ne_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r1, r0, lsr #17
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movwne r0, #1
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; CHECK-NEXT: bx lr
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%srl = lshr i64 %a, 17
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%cmp = icmp ne i64 %srl, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_eq_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r0, r1, lsl #17
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: bx lr
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%shl = shl i64 %a, 17
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%cmp = icmp eq i64 %shl, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_ne_zero:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r0, r1, lsl #17
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movwne r0, #1
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; CHECK-NEXT: bx lr
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%shl = shl i64 %a, 17
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%cmp = icmp ne i64 %shl, 0
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ret i1 %cmp
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}
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; Negative test: optimization should not be applied if shift has multiple users.
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define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i64 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: mov r4, r0
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; CHECK-NEXT: lsl r0, r1, #17
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; CHECK-NEXT: orr r5, r0, r4, lsr #15
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; CHECK-NEXT: lsl r0, r4, #17
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: bl use
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; CHECK-NEXT: orr r0, r5, r4, lsl #17
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: pop {r4, r5, r11, pc}
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%shl = shl i64 %a, 17
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%cmp = icmp eq i64 %shl, 0
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call void @use(i64 %shl)
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ret i1 %cmp
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}
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; Check that optimization is applied to DAG having appropriate shape
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; even if there were no actual shift's expansion.
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define i1 @opt_setcc_expanded_shl_correct_shifts(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: orr r0, r1, r0, lsl #17
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: bx lr
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%shl.a = shl i32 %a, 17
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%srl.b = lshr i32 %b, 15
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%or.0 = or i32 %shl.a, %srl.b
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%shl.b = shl i32 %b, 17
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%or.1 = or i32 %or.0, %shl.b
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%cmp = icmp eq i32 %or.1, 0
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ret i1 %cmp
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}
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; Negative test: optimization should not be applied as
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; constants used in shifts do not match.
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define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsl r0, r0, #17
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; CHECK-NEXT: orr r0, r0, r1, lsr #15
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; CHECK-NEXT: orr r0, r0, r1, lsl #18
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsr r0, r0, #5
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; CHECK-NEXT: bx lr
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%shl.a = shl i32 %a, 17
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%srl.b = lshr i32 %b, 15
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%or.0 = or i32 %shl.a, %srl.b
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%shl.b = shl i32 %b, 18
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%or.1 = or i32 %or.0, %shl.b
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%cmp = icmp eq i32 %or.1, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind {
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; CHECK-LABEL: opt_setcc_shl_ne_zero_i128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsl r3, r3, #17
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; CHECK-NEXT: orr r12, r3, r2, lsr #15
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; CHECK-NEXT: lsl r3, r1, #17
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; CHECK-NEXT: orr r3, r3, r0, lsr #15
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; CHECK-NEXT: orr r0, r2, r0
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; CHECK-NEXT: orr r3, r3, r12
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; CHECK-NEXT: lsl r0, r0, #17
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; CHECK-NEXT: orr r0, r0, r1, lsr #15
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; CHECK-NEXT: orrs r0, r0, r3
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; CHECK-NEXT: movwne r0, #1
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; CHECK-NEXT: bx lr
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%shl = shl i128 %a, 17
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%cmp = icmp ne i128 %shl, 0
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ret i1 %cmp
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}
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declare void @use(i64 %a)
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