766ca2c59e
VSX introduced some permute instructions that are direct replacements for Altivec ones except they can target all the VSX registers. We have added code generation for most of these but somehow missed the low/hi word merges (XXMRG[LH]W). This caused some additional spills on some large computationally intensive code. This patch simply adds the missed patterns.
111 lines
3.4 KiB
LLVM
111 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE
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define <8 x i16> @pr25080(<8 x i32> %a) {
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; LE-LABEL: pr25080:
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; LE: # %bb.0: # %entry
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; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; LE-NEXT: xxlxor 37, 37, 37
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; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; LE-NEXT: lvx 4, 0, 3
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; LE-NEXT: xxland 34, 34, 36
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; LE-NEXT: xxland 35, 35, 36
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; LE-NEXT: vcmpequw 2, 2, 5
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; LE-NEXT: vcmpequw 3, 3, 5
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; LE-NEXT: xxswapd 0, 34
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; LE-NEXT: mfvsrwz 3, 34
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; LE-NEXT: xxsldwi 1, 34, 34, 1
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; LE-NEXT: mfvsrwz 4, 35
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; LE-NEXT: xxsldwi 2, 34, 34, 3
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; LE-NEXT: mtvsrd 36, 3
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; LE-NEXT: mffprwz 3, 0
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; LE-NEXT: xxswapd 0, 35
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; LE-NEXT: mtvsrd 37, 4
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; LE-NEXT: mffprwz 4, 1
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; LE-NEXT: xxsldwi 1, 35, 35, 1
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; LE-NEXT: mtvsrd 34, 3
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; LE-NEXT: mffprwz 3, 2
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; LE-NEXT: mtvsrd 32, 4
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; LE-NEXT: mffprwz 4, 0
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; LE-NEXT: xxsldwi 0, 35, 35, 3
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; LE-NEXT: mtvsrd 33, 3
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; LE-NEXT: mffprwz 3, 1
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; LE-NEXT: mtvsrd 38, 4
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; LE-NEXT: mtvsrd 35, 3
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; LE-NEXT: mffprwz 3, 0
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; LE-NEXT: vmrghh 2, 0, 2
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; LE-NEXT: mtvsrd 32, 3
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; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; LE-NEXT: vmrghh 4, 1, 4
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; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; LE-NEXT: vmrghh 3, 3, 6
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; LE-NEXT: vmrghh 5, 0, 5
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; LE-NEXT: xxmrglw 0, 36, 34
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; LE-NEXT: vspltish 4, 15
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; LE-NEXT: xxmrglw 1, 37, 35
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; LE-NEXT: lvx 3, 0, 3
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; LE-NEXT: xxmrgld 34, 1, 0
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; LE-NEXT: xxlor 34, 34, 35
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; LE-NEXT: vslh 2, 2, 4
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; LE-NEXT: vsrah 2, 2, 4
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; LE-NEXT: blr
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;
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; BE-LABEL: pr25080:
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; BE: # %bb.0: # %entry
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; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; BE-NEXT: xxlxor 36, 36, 36
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; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; BE-NEXT: lxvw4x 0, 0, 3
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; BE-NEXT: xxland 35, 35, 0
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; BE-NEXT: xxland 34, 34, 0
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; BE-NEXT: vcmpequw 3, 3, 4
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; BE-NEXT: vcmpequw 2, 2, 4
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; BE-NEXT: xxswapd 0, 35
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; BE-NEXT: mfvsrwz 3, 35
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; BE-NEXT: xxsldwi 1, 35, 35, 1
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; BE-NEXT: mfvsrwz 4, 34
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; BE-NEXT: mtvsrwz 36, 3
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; BE-NEXT: xxsldwi 2, 35, 35, 3
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; BE-NEXT: mffprwz 3, 0
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; BE-NEXT: xxswapd 0, 34
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; BE-NEXT: mtvsrwz 35, 4
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; BE-NEXT: mffprwz 4, 1
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; BE-NEXT: xxsldwi 1, 34, 34, 1
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; BE-NEXT: mtvsrwz 37, 3
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; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; BE-NEXT: mtvsrwz 32, 4
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; BE-NEXT: mffprwz 4, 0
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; BE-NEXT: lxvw4x 33, 0, 3
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; BE-NEXT: xxsldwi 0, 34, 34, 3
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; BE-NEXT: mffprwz 3, 1
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; BE-NEXT: mffprwz 5, 2
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; BE-NEXT: vperm 2, 0, 5, 1
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; BE-NEXT: mtvsrwz 37, 3
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; BE-NEXT: mffprwz 3, 0
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; BE-NEXT: mtvsrwz 38, 5
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; BE-NEXT: mtvsrwz 39, 4
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; BE-NEXT: mtvsrwz 32, 3
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; BE-NEXT: addis 3, 2, .LCPI0_2@toc@ha
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; BE-NEXT: vperm 4, 6, 4, 1
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; BE-NEXT: addi 3, 3, .LCPI0_2@toc@l
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; BE-NEXT: vperm 5, 5, 7, 1
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; BE-NEXT: vperm 3, 0, 3, 1
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; BE-NEXT: xxmrghw 0, 36, 34
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; BE-NEXT: xxmrghw 1, 35, 37
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; BE-NEXT: vspltish 3, 15
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; BE-NEXT: xxmrghd 34, 1, 0
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; BE-NEXT: lxvw4x 0, 0, 3
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; BE-NEXT: xxlor 34, 34, 0
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; BE-NEXT: vslh 2, 2, 3
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; BE-NEXT: vsrah 2, 2, 3
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; BE-NEXT: blr
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entry:
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%0 = trunc <8 x i32> %a to <8 x i23>
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%1 = icmp eq <8 x i23> %0, zeroinitializer
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%2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
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%3 = sext <8 x i1> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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