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clang-p2996/llvm/test/CodeGen/RISCV/bittest.ll
Craig Topper 0ebb02b90a [RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd. 
This hook determines if SimplifySetcc transforms (X & (C l>>/<< Y))
==/!= 0 into ((X <</l>> Y) & C) ==/!= 0. Where C is a constant and
X might be a constant.

The default implementation favors doing the transform if X is not
a constant. Otherwise the code is left alone. There is a provision
that if the target supports a bit test instruction then the transform
will favor ((1 << Y) & X) ==/!= 0. RISCV does not say it has a variable
bit test operation.

RISCV with Zbs does have a BEXT instruction that performs (X >> Y) & 1.
Without Zbs, (X >> Y) & 1 still looks preferable to ((1 << Y) & X) since
we can fold use ANDI instead of putting a 1 in a register for SLL.

This patch overrides this hook to favor bit extract patterns and
otherwise falls back to the "do the transform if X is not a constant"
heuristic.

I've added tests where both C and X are constants with both the shl form
and lshr form. I've also added a test for a switch statement that lowers
to a bit test. That was my original motivation for looking at this.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D124639
2022-05-11 11:13:17 -07:00

439 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV32,RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,NOZBS,RV64,RV64I
; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
; CHECK-LABEL: bittest_7_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 128
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%shr = lshr i32 %a, 7
%not = xor i32 %shr, -1
%and = and i32 %not, 1
ret i32 %and
}
define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
; CHECK-LABEL: bittest_10_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1024
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%shr = lshr i32 %a, 10
%not = xor i32 %shr, -1
%and = and i32 %not, 1
ret i32 %and
}
define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
; NOZBS-LABEL: bittest_11_i32:
; NOZBS: # %bb.0:
; NOZBS-NEXT: srli a0, a0, 11
; NOZBS-NEXT: not a0, a0
; NOZBS-NEXT: andi a0, a0, 1
; NOZBS-NEXT: ret
;
; ZBS-LABEL: bittest_11_i32:
; ZBS: # %bb.0:
; ZBS-NEXT: bexti a0, a0, 11
; ZBS-NEXT: xori a0, a0, 1
; ZBS-NEXT: ret
%shr = lshr i32 %a, 11
%not = xor i32 %shr, -1
%and = and i32 %not, 1
ret i32 %and
}
define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
; RV32-LABEL: bittest_31_i32:
; RV32: # %bb.0:
; RV32-NEXT: not a0, a0
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: ret
;
; RV64-LABEL: bittest_31_i32:
; RV64: # %bb.0:
; RV64-NEXT: not a0, a0
; RV64-NEXT: srliw a0, a0, 31
; RV64-NEXT: ret
%shr = lshr i32 %a, 31
%not = xor i32 %shr, -1
%and = and i32 %not, 1
ret i32 %and
}
define i64 @bittest_7_i64(i64 %a) nounwind {
; RV32-LABEL: bittest_7_i64:
; RV32: # %bb.0:
; RV32-NEXT: andi a0, a0, 128
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: li a1, 0
; RV32-NEXT: ret
;
; RV64-LABEL: bittest_7_i64:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, 128
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
%shr = lshr i64 %a, 7
%not = xor i64 %shr, -1
%and = and i64 %not, 1
ret i64 %and
}
define i64 @bittest_10_i64(i64 %a) nounwind {
; RV32-LABEL: bittest_10_i64:
; RV32: # %bb.0:
; RV32-NEXT: andi a0, a0, 1024
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: li a1, 0
; RV32-NEXT: ret
;
; RV64-LABEL: bittest_10_i64:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, 1024
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret
%shr = lshr i64 %a, 10
%not = xor i64 %shr, -1
%and = and i64 %not, 1
ret i64 %and
}
define i64 @bittest_11_i64(i64 %a) nounwind {
; RV32I-LABEL: bittest_11_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 11
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: bittest_11_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 11
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV32ZBS-LABEL: bittest_11_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bexti a0, a0, 11
; RV32ZBS-NEXT: xori a0, a0, 1
; RV32ZBS-NEXT: li a1, 0
; RV32ZBS-NEXT: ret
;
; RV64ZBS-LABEL: bittest_11_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 11
; RV64ZBS-NEXT: xori a0, a0, 1
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, 11
%not = xor i64 %shr, -1
%and = and i64 %not, 1
ret i64 %and
}
define i64 @bittest_31_i64(i64 %a) nounwind {
; RV32-LABEL: bittest_31_i64:
; RV32: # %bb.0:
; RV32-NEXT: not a0, a0
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: li a1, 0
; RV32-NEXT: ret
;
; RV64I-LABEL: bittest_31_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bittest_31_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 31
; RV64ZBS-NEXT: xori a0, a0, 1
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, 31
%not = xor i64 %shr, -1
%and = and i64 %not, 1
ret i64 %and
}
define i64 @bittest_32_i64(i64 %a) nounwind {
; RV32-LABEL: bittest_32_i64:
; RV32: # %bb.0:
; RV32-NEXT: not a0, a1
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: li a1, 0
; RV32-NEXT: ret
;
; RV64I-LABEL: bittest_32_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bittest_32_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 32
; RV64ZBS-NEXT: xori a0, a0, 1
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, 32
%not = xor i64 %shr, -1
%and = and i64 %not, 1
ret i64 %and
}
define i64 @bittest_63_i64(i64 %a) nounwind {
; RV32-LABEL: bittest_63_i64:
; RV32: # %bb.0:
; RV32-NEXT: not a0, a1
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: li a1, 0
; RV32-NEXT: ret
;
; RV64-LABEL: bittest_63_i64:
; RV64: # %bb.0:
; RV64-NEXT: not a0, a0
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: ret
%shr = lshr i64 %a, 63
%not = xor i64 %shr, -1
%and = and i64 %not, 1
ret i64 %and
}
; Make sure we use (andi (srl X, Y), 1) or bext.
define i1 @bittest_constant_by_var_shr_i32(i32 signext %b) nounwind {
; RV32I-LABEL: bittest_constant_by_var_shr_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 301408
; RV32I-NEXT: addi a1, a1, 722
; RV32I-NEXT: srl a0, a1, a0
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: bittest_constant_by_var_shr_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV32ZBS-LABEL: bittest_constant_by_var_shr_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: lui a1, 301408
; RV32ZBS-NEXT: addi a1, a1, 722
; RV32ZBS-NEXT: bext a0, a1, a0
; RV32ZBS-NEXT: ret
;
; RV64ZBS-LABEL: bittest_constant_by_var_shr_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
%shl = lshr i32 1234567890, %b
%and = and i32 %shl, 1
%cmp = icmp ne i32 %and, 0
ret i1 %cmp
}
; Make sure we use (andi (srl X, Y), 1) or bext.
define i1 @bittest_constant_by_var_shl_i32(i32 signext %b) nounwind {
; RV32I-LABEL: bittest_constant_by_var_shl_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 301408
; RV32I-NEXT: addi a1, a1, 722
; RV32I-NEXT: srl a0, a1, a0
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: bittest_constant_by_var_shl_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV32ZBS-LABEL: bittest_constant_by_var_shl_i32:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: lui a1, 301408
; RV32ZBS-NEXT: addi a1, a1, 722
; RV32ZBS-NEXT: bext a0, a1, a0
; RV32ZBS-NEXT: ret
;
; RV64ZBS-LABEL: bittest_constant_by_var_shl_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%and = and i32 %shl, 1234567890
%cmp = icmp ne i32 %and, 0
ret i1 %cmp
}
; Make sure we use (andi (srl X, Y), 1) or bext.
define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
; RV32-LABEL: bittest_constant_by_var_shr_i64:
; RV32: # %bb.0:
; RV32-NEXT: addi a1, a0, -32
; RV32-NEXT: bltz a1, .LBB12_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: andi a0, zero, 1
; RV32-NEXT: ret
; RV32-NEXT: .LBB12_2:
; RV32-NEXT: lui a1, 301408
; RV32-NEXT: addi a1, a1, 722
; RV32-NEXT: srl a0, a1, a0
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: ret
;
; RV64I-LABEL: bittest_constant_by_var_shr_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: srl a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bittest_constant_by_var_shr_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
%shl = lshr i64 1234567890, %b
%and = and i64 %shl, 1
%cmp = icmp ne i64 %and, 0
ret i1 %cmp
}
; Make sure we use (andi (srl X, Y), 1) or bext.
define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
; RV32-LABEL: bittest_constant_by_var_shl_i64:
; RV32: # %bb.0:
; RV32-NEXT: addi a1, a0, -32
; RV32-NEXT: bltz a1, .LBB13_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: andi a0, zero, 1
; RV32-NEXT: ret
; RV32-NEXT: .LBB13_2:
; RV32-NEXT: lui a1, 301408
; RV32-NEXT: addi a1, a1, 722
; RV32-NEXT: srl a0, a1, a0
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: ret
;
; RV64I-LABEL: bittest_constant_by_var_shl_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 301408
; RV64I-NEXT: addiw a1, a1, 722
; RV64I-NEXT: srl a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bittest_constant_by_var_shl_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lui a1, 301408
; RV64ZBS-NEXT: addiw a1, a1, 722
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b
%and = and i64 %shl, 1234567890
%cmp = icmp ne i64 %and, 0
ret i1 %cmp
}
; We want to use (andi (srl X, Y), 1) or bext before the beqz.
define void @bittest_switch(i32 signext %0) {
; RV32I-LABEL: bittest_switch:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 31
; RV32I-NEXT: bltu a1, a0, .LBB14_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: lui a1, 524291
; RV32I-NEXT: addi a1, a1, 768
; RV32I-NEXT: srl a0, a1, a0
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: beqz a0, .LBB14_3
; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: tail bar@plt
; RV32I-NEXT: .LBB14_3:
; RV32I-NEXT: ret
;
; RV64I-LABEL: bittest_switch:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 31
; RV64I-NEXT: bltu a1, a0, .LBB14_3
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: lui a1, 2048
; RV64I-NEXT: addiw a1, a1, 51
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: srl a0, a1, a0
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB14_3
; RV64I-NEXT: # %bb.2:
; RV64I-NEXT: tail bar@plt
; RV64I-NEXT: .LBB14_3:
; RV64I-NEXT: ret
;
; RV32ZBS-LABEL: bittest_switch:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: li a1, 31
; RV32ZBS-NEXT: bltu a1, a0, .LBB14_3
; RV32ZBS-NEXT: # %bb.1:
; RV32ZBS-NEXT: lui a1, 524291
; RV32ZBS-NEXT: addi a1, a1, 768
; RV32ZBS-NEXT: bext a0, a1, a0
; RV32ZBS-NEXT: beqz a0, .LBB14_3
; RV32ZBS-NEXT: # %bb.2:
; RV32ZBS-NEXT: tail bar@plt
; RV32ZBS-NEXT: .LBB14_3:
; RV32ZBS-NEXT: ret
;
; RV64ZBS-LABEL: bittest_switch:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: li a1, 31
; RV64ZBS-NEXT: bltu a1, a0, .LBB14_3
; RV64ZBS-NEXT: # %bb.1:
; RV64ZBS-NEXT: lui a1, 2048
; RV64ZBS-NEXT: addiw a1, a1, 51
; RV64ZBS-NEXT: slli a1, a1, 8
; RV64ZBS-NEXT: bext a0, a1, a0
; RV64ZBS-NEXT: beqz a0, .LBB14_3
; RV64ZBS-NEXT: # %bb.2:
; RV64ZBS-NEXT: tail bar@plt
; RV64ZBS-NEXT: .LBB14_3:
; RV64ZBS-NEXT: ret
switch i32 %0, label %3 [
i32 8, label %2
i32 9, label %2
i32 12, label %2
i32 13, label %2
i32 31, label %2
]
2:
tail call void @bar()
br label %3
3:
ret void
}
declare void @bar()
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