aaad507546
When lowering GlobalAddressNodes, we were removing a non-zero offset and creating a separate ADD. It already comes out of SelectionDAGBuilder with a separate ADD. The ADD was being removed by DAGCombiner. This patch disables the DAG combine so we don't have to reverse it. Test changes all look to be instruction order changes. Probably due to different DAG node ordering. Differential Revision: https://reviews.llvm.org/D126558
185 lines
5.9 KiB
LLVM
185 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
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define half @flh(half *%a) nounwind {
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; RV32IZFH-LABEL: flh:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flh ft0, 0(a0)
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; RV32IZFH-NEXT: flh ft1, 6(a0)
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; RV32IZFH-NEXT: fadd.h fa0, ft0, ft1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: flh:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flh ft0, 0(a0)
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; RV64IZFH-NEXT: flh ft1, 6(a0)
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; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1
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; RV64IZFH-NEXT: ret
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%1 = load half, half* %a
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%2 = getelementptr half, half* %a, i32 3
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%3 = load half, half* %2
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; Use both loaded values in an FP op to ensure an flh is used, even for the
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; soft half ABI
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%4 = fadd half %1, %3
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ret half %4
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}
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define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
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; Use %b and %c in an FP op to ensure half precision floating point registers
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; are used, even for the soft half ABI
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; RV32IZFH-LABEL: fsh:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV32IZFH-NEXT: fsh ft0, 0(a0)
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; RV32IZFH-NEXT: fsh ft0, 16(a0)
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsh:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fsh ft0, 0(a0)
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; RV64IZFH-NEXT: fsh ft0, 16(a0)
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; RV64IZFH-NEXT: ret
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%1 = fadd half %b, %c
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store half %1, half* %a
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%2 = getelementptr half, half* %a, i32 8
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store half %1, half* %2
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ret void
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}
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; Check load and store to a global
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@G = dso_local global half 0.0
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define half @flh_fsh_global(half %a, half %b) nounwind {
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; Use %a and %b in an FP op to ensure half precision floating point registers
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; are used, even for the soft half ABI
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; RV32IZFH-LABEL: flh_fsh_global:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
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; RV32IZFH-NEXT: lui a0, %hi(G)
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; RV32IZFH-NEXT: flh ft0, %lo(G)(a0)
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; RV32IZFH-NEXT: addi a1, a0, %lo(G)
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; RV32IZFH-NEXT: fsh fa0, %lo(G)(a0)
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; RV32IZFH-NEXT: flh ft0, 18(a1)
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; RV32IZFH-NEXT: fsh fa0, 18(a1)
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: flh_fsh_global:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
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; RV64IZFH-NEXT: lui a0, %hi(G)
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; RV64IZFH-NEXT: flh ft0, %lo(G)(a0)
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; RV64IZFH-NEXT: addi a1, a0, %lo(G)
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; RV64IZFH-NEXT: fsh fa0, %lo(G)(a0)
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; RV64IZFH-NEXT: flh ft0, 18(a1)
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; RV64IZFH-NEXT: fsh fa0, 18(a1)
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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%2 = load volatile half, half* @G
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store half %1, half* @G
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%3 = getelementptr half, half* @G, i32 9
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%4 = load volatile half, half* %3
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store half %1, half* %3
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ret half %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define half @flh_fsh_constant(half %a) nounwind {
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; RV32IZFH-LABEL: flh_fsh_constant:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: lui a0, 912092
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; RV32IZFH-NEXT: flh ft0, -273(a0)
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; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0
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; RV32IZFH-NEXT: fsh fa0, -273(a0)
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: flh_fsh_constant:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: lui a0, 228023
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; RV64IZFH-NEXT: slli a0, a0, 2
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; RV64IZFH-NEXT: flh ft0, -273(a0)
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; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0
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; RV64IZFH-NEXT: fsh fa0, -273(a0)
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; RV64IZFH-NEXT: ret
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%1 = inttoptr i32 3735928559 to half*
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%2 = load volatile half, half* %1
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%3 = fadd half %a, %2
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store half %3, half* %1
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ret half %3
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}
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declare void @notdead(i8*)
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define half @flh_stack(half %a) nounwind {
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; RV32IZFH-LABEL: flh_stack:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fmv.h fs0, fa0
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; RV32IZFH-NEXT: addi a0, sp, 4
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; RV32IZFH-NEXT: call notdead@plt
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; RV32IZFH-NEXT: flh ft0, 4(sp)
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; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: flh_stack:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
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; RV64IZFH-NEXT: fmv.h fs0, fa0
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; RV64IZFH-NEXT: mv a0, sp
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; RV64IZFH-NEXT: call notdead@plt
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; RV64IZFH-NEXT: flh ft0, 0(sp)
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; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = alloca half, align 4
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%2 = bitcast half* %1 to i8*
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call void @notdead(i8* %2)
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%3 = load half, half* %1
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%4 = fadd half %3, %a ; force load in to FPR16
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ret half %4
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}
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define dso_local void @fsh_stack(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fsh_stack:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV32IZFH-NEXT: fsh ft0, 8(sp)
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; RV32IZFH-NEXT: addi a0, sp, 8
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; RV32IZFH-NEXT: call notdead@plt
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsh_stack:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fsh ft0, 4(sp)
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; RV64IZFH-NEXT: addi a0, sp, 4
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; RV64IZFH-NEXT: call notdead@plt
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b ; force store from FPR16
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%2 = alloca half, align 4
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store half %1, half* %2
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%3 = bitcast half* %2 to i8*
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call void @notdead(i8* %3)
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ret void
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}
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