8a3b6ba756
A RISCV implementation can choose to implement unaligned load/store support. We currently don't have a way for such a processor to indicate a preference for unaligned load/stores, so add a subtarget feature. There doesn't appear to be a formal extension for unaligned support. The RISCV Profiles (https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva20u64-profile) docs use the name Zicclsm, but a) that doesn't appear to actually been standardized, and b) isn't quite what we want here anyway due to the perf comment. Instead, we can follow precedent from other backends and have a feature flag for the existence of misaligned load/stores with sufficient performance that user code should actually use them. Differential Revision: https://reviews.llvm.org/D126085
284 lines
7.8 KiB
LLVM
284 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,NOMISALIGN,RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,NOMISALIGN,RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,MISALIGN,MISALIGN-RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=ALL,MISALIGN,MISALIGN-RV64I %s
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; A collection of cases showing codegen for unaligned loads and stores
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define i8 @load_i8(i8* %p) {
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; ALL-LABEL: load_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: lb a0, 0(a0)
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; ALL-NEXT: ret
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%res = load i8, i8* %p, align 1
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ret i8 %res
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}
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define i16 @load_i16(i16* %p) {
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; NOMISALIGN-LABEL: load_i16:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: lb a1, 1(a0)
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; NOMISALIGN-NEXT: lbu a0, 0(a0)
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; NOMISALIGN-NEXT: slli a1, a1, 8
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; NOMISALIGN-NEXT: or a0, a1, a0
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: load_i16:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: lh a0, 0(a0)
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; MISALIGN-NEXT: ret
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%res = load i16, i16* %p, align 1
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ret i16 %res
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}
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define i24 @load_i24(i24* %p) {
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; NOMISALIGN-LABEL: load_i24:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: lbu a1, 1(a0)
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; NOMISALIGN-NEXT: lbu a2, 0(a0)
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; NOMISALIGN-NEXT: lb a0, 2(a0)
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; NOMISALIGN-NEXT: slli a1, a1, 8
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; NOMISALIGN-NEXT: or a1, a1, a2
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; NOMISALIGN-NEXT: slli a0, a0, 16
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; NOMISALIGN-NEXT: or a0, a1, a0
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: load_i24:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: lb a1, 2(a0)
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; MISALIGN-NEXT: lhu a0, 0(a0)
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; MISALIGN-NEXT: slli a1, a1, 16
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; MISALIGN-NEXT: or a0, a0, a1
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; MISALIGN-NEXT: ret
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%res = load i24, i24* %p, align 1
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ret i24 %res
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}
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define i32 @load_i32(i32* %p) {
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; RV32I-LABEL: load_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a2, 0(a0)
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; RV32I-NEXT: lbu a3, 3(a0)
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; RV32I-NEXT: lbu a0, 2(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: slli a2, a3, 8
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; RV32I-NEXT: or a0, a2, a0
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a2, 0(a0)
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; RV64I-NEXT: lb a3, 3(a0)
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; RV64I-NEXT: lbu a0, 2(a0)
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a2, a3, 8
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; RV64I-NEXT: or a0, a2, a0
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; RV64I-NEXT: slli a0, a0, 16
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; MISALIGN-LABEL: load_i32:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: lw a0, 0(a0)
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; MISALIGN-NEXT: ret
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%res = load i32, i32* %p, align 1
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ret i32 %res
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}
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define i64 @load_i64(i64* %p) {
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; RV32I-LABEL: load_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lbu a1, 1(a0)
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; RV32I-NEXT: lbu a2, 0(a0)
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; RV32I-NEXT: lbu a3, 3(a0)
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; RV32I-NEXT: lbu a4, 2(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: slli a2, a3, 8
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; RV32I-NEXT: or a2, a2, a4
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; RV32I-NEXT: slli a2, a2, 16
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; RV32I-NEXT: or a2, a2, a1
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; RV32I-NEXT: lbu a1, 5(a0)
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; RV32I-NEXT: lbu a3, 4(a0)
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; RV32I-NEXT: lbu a4, 7(a0)
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; RV32I-NEXT: lbu a0, 6(a0)
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: slli a3, a4, 8
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; RV32I-NEXT: or a0, a3, a0
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: or a1, a0, a1
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: load_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a2, 0(a0)
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; RV64I-NEXT: lbu a3, 3(a0)
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; RV64I-NEXT: lbu a4, 2(a0)
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a1, a1, a2
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; RV64I-NEXT: slli a2, a3, 8
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; RV64I-NEXT: or a2, a2, a4
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; RV64I-NEXT: slli a2, a2, 16
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; RV64I-NEXT: or a1, a2, a1
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; RV64I-NEXT: lbu a2, 5(a0)
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; RV64I-NEXT: lbu a3, 4(a0)
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; RV64I-NEXT: lbu a4, 7(a0)
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; RV64I-NEXT: lbu a0, 6(a0)
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; RV64I-NEXT: slli a2, a2, 8
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; RV64I-NEXT: or a2, a2, a3
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; RV64I-NEXT: slli a3, a4, 8
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; RV64I-NEXT: or a0, a3, a0
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; RV64I-NEXT: slli a0, a0, 16
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; MISALIGN-RV32I-LABEL: load_i64:
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; MISALIGN-RV32I: # %bb.0:
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; MISALIGN-RV32I-NEXT: lw a2, 0(a0)
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; MISALIGN-RV32I-NEXT: lw a1, 4(a0)
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; MISALIGN-RV32I-NEXT: mv a0, a2
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; MISALIGN-RV32I-NEXT: ret
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;
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; MISALIGN-RV64I-LABEL: load_i64:
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; MISALIGN-RV64I: # %bb.0:
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; MISALIGN-RV64I-NEXT: ld a0, 0(a0)
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; MISALIGN-RV64I-NEXT: ret
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%res = load i64, i64* %p, align 1
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ret i64 %res
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}
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define void @store_i8(i8* %p, i8 %v) {
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; ALL-LABEL: store_i8:
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; ALL: # %bb.0:
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; ALL-NEXT: sb a1, 0(a0)
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; ALL-NEXT: ret
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store i8 %v, i8* %p, align 1
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ret void
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}
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define void @store_i16(i16* %p, i16 %v) {
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; NOMISALIGN-LABEL: store_i16:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: sb a1, 0(a0)
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; NOMISALIGN-NEXT: srli a1, a1, 8
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; NOMISALIGN-NEXT: sb a1, 1(a0)
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: store_i16:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: sh a1, 0(a0)
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; MISALIGN-NEXT: ret
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store i16 %v, i16* %p, align 1
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ret void
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}
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define void @store_i24(i24* %p, i24 %v) {
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; NOMISALIGN-LABEL: store_i24:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: sb a1, 0(a0)
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; NOMISALIGN-NEXT: srli a2, a1, 8
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; NOMISALIGN-NEXT: sb a2, 1(a0)
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; NOMISALIGN-NEXT: srli a1, a1, 16
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; NOMISALIGN-NEXT: sb a1, 2(a0)
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: store_i24:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: sh a1, 0(a0)
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; MISALIGN-NEXT: srli a1, a1, 16
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; MISALIGN-NEXT: sb a1, 2(a0)
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; MISALIGN-NEXT: ret
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store i24 %v, i24* %p, align 1
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ret void
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}
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define void @store_i32(i32* %p, i32 %v) {
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; NOMISALIGN-LABEL: store_i32:
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; NOMISALIGN: # %bb.0:
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; NOMISALIGN-NEXT: sb a1, 0(a0)
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; NOMISALIGN-NEXT: srli a2, a1, 24
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; NOMISALIGN-NEXT: sb a2, 3(a0)
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; NOMISALIGN-NEXT: srli a2, a1, 16
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; NOMISALIGN-NEXT: sb a2, 2(a0)
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; NOMISALIGN-NEXT: srli a1, a1, 8
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; NOMISALIGN-NEXT: sb a1, 1(a0)
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; NOMISALIGN-NEXT: ret
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;
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; MISALIGN-LABEL: store_i32:
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; MISALIGN: # %bb.0:
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; MISALIGN-NEXT: sw a1, 0(a0)
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; MISALIGN-NEXT: ret
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store i32 %v, i32* %p, align 1
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ret void
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}
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define void @store_i64(i64* %p, i64 %v) {
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; RV32I-LABEL: store_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sb a2, 4(a0)
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: srli a3, a2, 24
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; RV32I-NEXT: sb a3, 7(a0)
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; RV32I-NEXT: srli a3, a2, 16
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; RV32I-NEXT: sb a3, 6(a0)
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; RV32I-NEXT: srli a2, a2, 8
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; RV32I-NEXT: sb a2, 5(a0)
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; RV32I-NEXT: srli a2, a1, 24
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; RV32I-NEXT: sb a2, 3(a0)
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; RV32I-NEXT: srli a2, a1, 16
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; RV32I-NEXT: sb a2, 2(a0)
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; RV32I-NEXT: srli a1, a1, 8
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; RV32I-NEXT: sb a1, 1(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: store_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sb a1, 0(a0)
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; RV64I-NEXT: srli a2, a1, 56
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; RV64I-NEXT: sb a2, 7(a0)
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; RV64I-NEXT: srli a2, a1, 48
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; RV64I-NEXT: sb a2, 6(a0)
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; RV64I-NEXT: srli a2, a1, 40
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; RV64I-NEXT: sb a2, 5(a0)
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; RV64I-NEXT: srli a2, a1, 32
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; RV64I-NEXT: sb a2, 4(a0)
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; RV64I-NEXT: srli a2, a1, 24
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; RV64I-NEXT: sb a2, 3(a0)
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; RV64I-NEXT: srli a2, a1, 16
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; RV64I-NEXT: sb a2, 2(a0)
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; RV64I-NEXT: srli a1, a1, 8
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; RV64I-NEXT: sb a1, 1(a0)
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; RV64I-NEXT: ret
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;
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; MISALIGN-RV32I-LABEL: store_i64:
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; MISALIGN-RV32I: # %bb.0:
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; MISALIGN-RV32I-NEXT: sw a2, 4(a0)
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; MISALIGN-RV32I-NEXT: sw a1, 0(a0)
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; MISALIGN-RV32I-NEXT: ret
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;
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; MISALIGN-RV64I-LABEL: store_i64:
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; MISALIGN-RV64I: # %bb.0:
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; MISALIGN-RV64I-NEXT: sd a1, 0(a0)
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; MISALIGN-RV64I-NEXT: ret
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store i64 %v, i64* %p, align 1
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ret void
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}
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