06fad8bc05
This is part of an ongoing effort toward making DAGCombine process the nodes in topological order. This is able to discover a couple of new optimizations, but also causes a couple of regression. I nevertheless chose to submit this patch for review as to start the discussion with people working on the backend so we can find a good way forward. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D124743
29 lines
976 B
LLVM
29 lines
976 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
|
|
|
|
; The and with -9 has multiple users which prevents
|
|
; SimplifyDemandedBits from touching it. The truncate only
|
|
; demands the lower 8 bits. X86ISelDAGToDAG.cpp wants form
|
|
; a test instruction from the icmp+trunc+and, but needs to
|
|
; mask the -9 to 8 bits since SimplifyDemandedBits didn't.
|
|
|
|
define i32 @foo(i16 signext %0, i32 %1, i32* nocapture %2) {
|
|
; CHECK-LABEL: foo:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: incl %edi
|
|
; CHECK-NEXT: andl $65527, %edi # imm = 0xFFF7
|
|
; CHECK-NEXT: movl %edi, (%rdx)
|
|
; CHECK-NEXT: xorl %eax, %eax
|
|
; CHECK-NEXT: testb %dil, %dil
|
|
; CHECK-NEXT: cmovel %esi, %eax
|
|
; CHECK-NEXT: retq
|
|
%4 = add i16 %0, 1
|
|
%5 = and i16 %4, -9
|
|
%6 = zext i16 %5 to i32
|
|
store i32 %6, i32* %2, align 4
|
|
%7 = trunc i16 %5 to i8
|
|
%8 = icmp eq i8 %7, 0
|
|
%9 = select i1 %8, i32 %1, i32 0
|
|
ret i32 %9
|
|
}
|