Serge Pavlov bdd0093f4d [GlobalISel] Add G_IS_FPCLASS ...

Add a generic opcode to represent `llvm.is_fpclass` intrinsic.

Differential Revision: https://reviews.llvm.org/D121454

2022-05-27 13:49:47 +07:00

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generic-vreg-undef-use.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

live-ins-01.mir

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live-ins-02.mir

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live-ins-03.mir

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test_copy_mismatch_types.mir

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test_copy_physregs_x86.mir

[X86] AVX512FP16 instructions enabling 1/6

2021-08-10 12:46:01 +08:00

test_copy.mir

[Test] Tidy up loose ends from LLVM_HAS_GLOBAL_ISEL

2020-08-27 16:36:27 +01:00

test_g_add.mir

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test_g_addrspacecast.mir

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test_g_assert_sext_register_bank_class.mir

GlobalISel: Relax handling of G_ASSERT_* with source register classes

2022-04-22 10:49:50 -04:00

test_g_assert_sext.mir

[GlobalISel] Add G_ASSERT_SEXT

2021-02-17 13:10:34 -08:00

test_g_assert_zext_register_bank_class.mir

GlobalISel: Relax handling of G_ASSERT_* with source register classes

2022-04-22 10:49:50 -04:00

test_g_assert_zext.mir

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test_g_bitcast.mir

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test_g_brindirect_is_indirect_branch.mir

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test_g_brjt_is_indirect_branch.mir

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test_g_brjt.mir

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test_g_build_vector_trunc.mir

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test_g_build_vector.mir

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test_g_bzero.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

test_g_concat_vectors.mir

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test_g_constant.mir

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test_g_dyn_stackalloc.mir

Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""

2020-02-13 10:16:06 -08:00

test_g_extract.mir

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test_g_fcmp.mir

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test_g_fconstant.mir

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test_g_icmp.mir

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test_g_insert.mir

[Test] Tidy up loose ends from LLVM_HAS_GLOBAL_ISEL

2020-08-27 16:36:27 +01:00

test_g_intrinsic_w_side_effects.mir

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test_g_intrinsic.mir

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test_g_inttoptr.mir

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test_g_is_fpclass.mir

[GlobalISel] Add G_IS_FPCLASS

2022-05-27 13:49:47 +07:00

test_g_jump_table.mir

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test_g_llround.mir

[GlobalISel] Add G_LLROUND

2021-08-20 14:07:21 -07:00

test_g_load.mir

GlobalISel: Verify atomic load/store ordering restriction

2022-04-11 20:12:22 -04:00

test_g_lround.mir

[GlobalISel] Add G_LLROUND

2021-08-20 14:07:21 -07:00

test_g_memcpy_inline.mir

[GISel] Support llvm.memcpy.inline

2021-06-30 12:39:05 -07:00

test_g_memcpy.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

test_g_memmove.mir

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test_g_memset.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

test_g_merge_values.mir

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test_g_phi.mir

[Test] Tidy up loose ends from LLVM_HAS_GLOBAL_ISEL

2020-08-27 16:36:27 +01:00

test_g_ptr_add.mir

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test_g_ptrmask.mir

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test_g_ptrtoint.mir

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test_g_rotr_rotl.mir

[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR

2021-12-21 11:59:33 +00:00

test_g_select.mir

[Test] Tidy up loose ends from LLVM_HAS_GLOBAL_ISEL

2020-08-27 16:36:27 +01:00

test_g_sext_inreg.mir

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test_g_sextload.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

test_g_shift.mir

[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR

2021-12-21 11:59:33 +00:00

test_g_shuffle_vector.mir

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test_g_store.mir

GlobalISel: Verify atomic load/store ordering restriction

2022-04-11 20:12:22 -04:00

test_g_trunc.mir

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test_g_ubfx_sbfx.mir

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test_g_zextload.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

test_insert_subreg.mir

[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs

2021-07-21 08:47:17 -07:00

test_phis_precede_nonphis.mir

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test_vector_reductions.mir

[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.

2021-08-19 16:38:52 -07:00

undef-should-only-be-set-on-subreg-defs.mir

MachineVerifier: Diagnose undef set on full register defs

2022-04-05 22:19:17 -04:00

verifier-generic-extend-truncate.mir

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verifier-generic-types-1.mir

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verifier-generic-types-2.mir

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verifier-implicit-virtreg-invalid-physreg-liveness.mir

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verifier-phi-fail0.mir

Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""

2020-02-13 10:16:06 -08:00

verifier-phi.mir

[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

2019-04-05 19:28:09 +00:00

verifier-pseudo-terminators.mir

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verifier-statepoint.mir

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verify-regbankselected-dbg-undef-use.mir

[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.

2021-12-05 15:55:59 -05:00

verify-regbankselected.mir

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verify-regops.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

verify-selected-dbg-undef-use.mir

[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.

2021-12-05 15:55:59 -05:00

verify-selected.mir

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