f31d39c42c
The transform was wrong in 3 ways:
1. It created an extra instruction when the source and dest types don't match.
2. It did not account for an extra use of the icmp, so could create 2 extra insts.
3. It favored bit hacks over icmp (icmp generally has better analysis).
This fixes #54692 (modeled by the PhaseOrdering tests).
This is a minimal step to fix the bug, but we should likely invert
this and the sibling transform for the "is negative" pattern too.
The backend should be able to invert this back to a shift if that
leads to better codegen.
This is a reduced try of 3794cc0e99 - that was reverted because
it could cause infinite loops by conflicting with the related
transforms in this block that create shifts.
100 lines
2.8 KiB
LLVM
100 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='default<O1>' -S < %s | FileCheck %s
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define i32 @PR38781(i32 noundef %a, i32 noundef %b) {
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; CHECK-LABEL: @PR38781(
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
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; CHECK-NEXT: [[AND:%.*]] = zext i1 [[TMP2]] to i32
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; CHECK-NEXT: ret i32 [[AND]]
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;
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%cmp = icmp sge i32 %a, 0
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%conv = zext i1 %cmp to i32
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%cmp1 = icmp sge i32 %b, 0
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%conv2 = zext i1 %cmp1 to i32
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%and = and i32 %conv, %conv2
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ret i32 %and
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}
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define i1 @PR54692_a(i8 noundef signext %c) #0 {
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; CHECK-LABEL: @PR54692_a(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[C:%.*]], 32
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; CHECK-NEXT: [[CMP5:%.*]] = icmp eq i8 [[C]], 127
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; CHECK-NEXT: [[OR1:%.*]] = or i1 [[TMP0]], [[CMP5]]
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; CHECK-NEXT: ret i1 [[OR1]]
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;
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entry:
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%conv = sext i8 %c to i32
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%cmp = icmp sge i32 %conv, 0
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br i1 %cmp, label %land.rhs, label %land.end
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land.rhs:
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%conv1 = sext i8 %c to i32
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%cmp2 = icmp sle i32 %conv1, 31
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br label %land.end
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land.end:
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%0 = phi i1 [ false, %entry ], [ %cmp2, %land.rhs ]
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%conv3 = zext i1 %0 to i32
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%conv4 = sext i8 %c to i32
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%cmp5 = icmp eq i32 %conv4, 127
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%conv6 = zext i1 %cmp5 to i32
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%or = or i32 %conv3, %conv6
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%tobool = icmp ne i32 %or, 0
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ret i1 %tobool
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}
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define i1 @PR54692_b(i8 noundef signext %c) {
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; CHECK-LABEL: @PR54692_b(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[C:%.*]], 32
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; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i8 [[C]], 127
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; CHECK-NEXT: [[OR2:%.*]] = or i1 [[TMP0]], [[CMP6]]
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; CHECK-NEXT: ret i1 [[OR2]]
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;
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entry:
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%conv = sext i8 %c to i32
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%cmp = icmp sge i32 %conv, 0
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%conv1 = zext i1 %cmp to i32
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%conv2 = sext i8 %c to i32
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%cmp3 = icmp sle i32 %conv2, 31
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%conv4 = zext i1 %cmp3 to i32
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%and = and i32 %conv1, %conv4
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%conv5 = sext i8 %c to i32
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%cmp6 = icmp eq i32 %conv5, 127
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%conv7 = zext i1 %cmp6 to i32
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%or = or i32 %and, %conv7
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%tobool = icmp ne i32 %or, 0
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ret i1 %tobool
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}
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define i1 @PR54692_c(i8 noundef signext %c) {
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; CHECK-LABEL: @PR54692_c(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i8 [[C:%.*]], 32
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; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i8 [[C]], 127
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; CHECK-NEXT: [[T0:%.*]] = or i1 [[TMP0]], [[CMP6]]
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; CHECK-NEXT: ret i1 [[T0]]
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;
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entry:
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%conv = sext i8 %c to i32
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%cmp = icmp sge i32 %conv, 0
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%conv1 = zext i1 %cmp to i32
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%conv2 = sext i8 %c to i32
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%cmp3 = icmp sle i32 %conv2, 31
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%conv4 = zext i1 %cmp3 to i32
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%and = and i32 %conv1, %conv4
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%tobool = icmp ne i32 %and, 0
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br i1 %tobool, label %lor.end, label %lor.rhs
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lor.rhs:
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%conv5 = sext i8 %c to i32
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%cmp6 = icmp eq i32 %conv5, 127
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br label %lor.end
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lor.end:
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%t0 = phi i1 [ true, %entry ], [ %cmp6, %lor.rhs ]
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ret i1 %t0
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}
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