ca79ff07d8
Reverts llvm/llvm-project#118734 There are currently some specific versions of MSVC that are miscompiling this code (we think). We don't know why as all the other build bots and at least some folks' local Windows builds work fine. This is a candidate revert to help the relevant folks catch their builders up and have time to debug the issue. However, the expectation is to roll forward at some point with a workaround if at all possible.
492 lines
15 KiB
C++
492 lines
15 KiB
C++
//===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares AMDGPU TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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#include "clang/Basic/TargetID.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/Support/AMDGPUAddrSpace.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/TargetParser/TargetParser.h"
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#include "llvm/TargetParser/Triple.h"
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#include <optional>
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
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static const char *const GCCRegNames[];
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static const LangASMap AMDGPUDefIsGenMap;
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static const LangASMap AMDGPUDefIsPrivMap;
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llvm::AMDGPU::GPUKind GPUKind;
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unsigned GPUFeatures;
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unsigned WavefrontSize;
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/// Whether to use cumode or WGP mode. True for cumode. False for WGP mode.
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bool CUMode;
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/// Whether having image instructions.
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bool HasImage = false;
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/// Target ID is device name followed by optional feature name postfixed
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/// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sramecc-.
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/// If the target ID contains feature+, map it to true.
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/// If the target ID contains feature-, map it to false.
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/// If the target ID does not contain a feature (default), do not map it.
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llvm::StringMap<bool> OffloadArchFeatures;
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std::string TargetID;
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bool hasFP64() const {
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return getTriple().getArch() == llvm::Triple::amdgcn ||
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!!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);
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}
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/// Has fast fma f32
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bool hasFastFMAF() const {
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return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_FMA_F32);
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}
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/// Has fast fma f64
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bool hasFastFMA() const {
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return getTriple().getArch() == llvm::Triple::amdgcn;
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}
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bool hasFMAF() const {
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return getTriple().getArch() == llvm::Triple::amdgcn ||
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!!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA);
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}
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bool hasFullRateDenormalsF32() const {
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return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32);
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}
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bool hasLDEXPF() const {
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return getTriple().getArch() == llvm::Triple::amdgcn ||
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!!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP);
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}
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static bool isAMDGCN(const llvm::Triple &TT) {
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return TT.getArch() == llvm::Triple::amdgcn;
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}
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static bool isR600(const llvm::Triple &TT) {
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return TT.getArch() == llvm::Triple::r600;
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}
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public:
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AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
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void setAddressSpaceMap(bool DefaultIsPrivate);
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void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
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uint64_t getPointerWidthV(LangAS AS) const override {
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if (isR600(getTriple()))
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return 32;
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unsigned TargetAS = getTargetAddressSpace(AS);
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if (TargetAS == llvm::AMDGPUAS::PRIVATE_ADDRESS ||
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TargetAS == llvm::AMDGPUAS::LOCAL_ADDRESS)
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return 32;
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return 64;
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}
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uint64_t getPointerAlignV(LangAS AddrSpace) const override {
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return getPointerWidthV(AddrSpace);
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}
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virtual bool isAddressSpaceSupersetOf(LangAS A, LangAS B) const override {
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// The flat address space AS(0) is a superset of all the other address
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// spaces used by the backend target.
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return A == B ||
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((A == LangAS::Default ||
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(isTargetAddressSpace(A) &&
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toTargetAddressSpace(A) == llvm::AMDGPUAS::FLAT_ADDRESS)) &&
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isTargetAddressSpace(B) &&
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toTargetAddressSpace(B) >= llvm::AMDGPUAS::FLAT_ADDRESS &&
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toTargetAddressSpace(B) <= llvm::AMDGPUAS::PRIVATE_ADDRESS &&
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toTargetAddressSpace(B) != llvm::AMDGPUAS::REGION_ADDRESS);
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}
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uint64_t getMaxPointerWidth() const override {
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return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
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}
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bool hasBFloat16Type() const override { return isAMDGCN(getTriple()); }
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std::string_view getClobbers() const override { return ""; }
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ArrayRef<const char *> getGCCRegNames() const override;
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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return {};
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}
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/// Accepted register names: (n, m is unsigned integer, n < m)
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/// v
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/// s
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/// a
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/// {vn}, {v[n]}
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/// {sn}, {s[n]}
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/// {an}, {a[n]}
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/// {S} , where S is a special register name
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////{v[n:m]}
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/// {s[n:m]}
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/// {a[n:m]}
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &Info) const override {
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static const ::llvm::StringSet<> SpecialRegs({
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"exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma",
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"flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo",
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"exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi",
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});
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switch (*Name) {
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case 'I':
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Info.setRequiresImmediate(-16, 64);
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return true;
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case 'J':
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Info.setRequiresImmediate(-32768, 32767);
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return true;
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case 'A':
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case 'B':
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case 'C':
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Info.setRequiresImmediate();
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return true;
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default:
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break;
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}
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StringRef S(Name);
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if (S == "DA" || S == "DB") {
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Name++;
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Info.setRequiresImmediate();
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return true;
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}
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bool HasLeftParen = S.consume_front("{");
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if (S.empty())
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return false;
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if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') {
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if (!HasLeftParen)
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return false;
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auto E = S.find('}');
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if (!SpecialRegs.count(S.substr(0, E)))
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return false;
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S = S.drop_front(E + 1);
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if (!S.empty())
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return false;
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// Found {S} where S is a special register.
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Info.setAllowsRegister();
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Name = S.data() - 1;
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return true;
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}
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S = S.drop_front();
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if (!HasLeftParen) {
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if (!S.empty())
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return false;
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// Found s, v or a.
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Info.setAllowsRegister();
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Name = S.data() - 1;
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return true;
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}
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bool HasLeftBracket = S.consume_front("[");
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unsigned long long N;
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if (S.empty() || consumeUnsignedInteger(S, 10, N))
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return false;
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if (S.consume_front(":")) {
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if (!HasLeftBracket)
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return false;
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unsigned long long M;
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if (consumeUnsignedInteger(S, 10, M) || N >= M)
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return false;
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}
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if (HasLeftBracket) {
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if (!S.consume_front("]"))
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return false;
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}
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if (!S.consume_front("}"))
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return false;
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if (!S.empty())
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return false;
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// Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]}
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// or {a[n:m]}.
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Info.setAllowsRegister();
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Name = S.data() - 1;
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return true;
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}
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// \p Constraint will be left pointing at the last character of
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// the constraint. In practice, it won't be changed unless the
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// constraint is longer than one character.
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std::string convertConstraint(const char *&Constraint) const override {
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StringRef S(Constraint);
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if (S == "DA" || S == "DB") {
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return std::string("^") + std::string(Constraint++, 2);
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}
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const char *Begin = Constraint;
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TargetInfo::ConstraintInfo Info("", "");
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if (validateAsmConstraint(Constraint, Info))
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return std::string(Begin).substr(0, Constraint - Begin + 1);
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Constraint = Begin;
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return std::string(1, *Constraint);
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}
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bool
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initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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StringRef CPU,
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const std::vector<std::string> &FeatureVec) const override;
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ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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bool useFP16ConversionIntrinsics() const override { return false; }
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::CharPtrBuiltinVaList;
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}
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bool isValidCPUName(StringRef Name) const override {
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if (getTriple().getArch() == llvm::Triple::amdgcn)
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return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;
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return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;
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}
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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if (getTriple().getArch() == llvm::Triple::amdgcn) {
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GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);
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GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);
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} else {
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GPUKind = llvm::AMDGPU::parseArchR600(Name);
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GPUFeatures = llvm::AMDGPU::getArchAttrR600(GPUKind);
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}
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return GPUKind != llvm::AMDGPU::GK_NONE;
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}
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void setSupportedOpenCLOpts() override {
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auto &Opts = getSupportedOpenCLOpts();
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Opts["cl_clang_storage_class_specifiers"] = true;
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Opts["__cl_clang_variadic_functions"] = true;
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Opts["__cl_clang_function_pointers"] = true;
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Opts["__cl_clang_non_portable_kernel_param_types"] = true;
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Opts["__cl_clang_bitfields"] = true;
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bool IsAMDGCN = isAMDGCN(getTriple());
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Opts["cl_khr_fp64"] = hasFP64();
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Opts["__opencl_c_fp64"] = hasFP64();
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if (IsAMDGCN || GPUKind >= llvm::AMDGPU::GK_CEDAR) {
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Opts["cl_khr_byte_addressable_store"] = true;
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Opts["cl_khr_global_int32_base_atomics"] = true;
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Opts["cl_khr_global_int32_extended_atomics"] = true;
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Opts["cl_khr_local_int32_base_atomics"] = true;
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Opts["cl_khr_local_int32_extended_atomics"] = true;
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}
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if (IsAMDGCN) {
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Opts["cl_khr_fp16"] = true;
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Opts["cl_khr_int64_base_atomics"] = true;
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Opts["cl_khr_int64_extended_atomics"] = true;
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Opts["cl_khr_mipmap_image"] = true;
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Opts["cl_khr_mipmap_image_writes"] = true;
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Opts["cl_khr_subgroups"] = true;
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Opts["cl_amd_media_ops"] = true;
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Opts["cl_amd_media_ops2"] = true;
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Opts["__opencl_c_images"] = true;
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Opts["__opencl_c_3d_image_writes"] = true;
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Opts["cl_khr_3d_image_writes"] = true;
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}
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}
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LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override {
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switch (TK) {
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case OCLTK_Image:
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return LangAS::opencl_constant;
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case OCLTK_ClkEvent:
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case OCLTK_Queue:
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case OCLTK_ReserveID:
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return LangAS::opencl_global;
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default:
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return TargetInfo::getOpenCLTypeAddrSpace(TK);
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}
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}
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LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override {
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switch (AS) {
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case 0:
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return LangAS::opencl_generic;
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case 1:
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return LangAS::opencl_global;
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case 3:
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return LangAS::opencl_local;
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case 4:
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return LangAS::opencl_constant;
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case 5:
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return LangAS::opencl_private;
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default:
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return getLangASFromTargetAS(AS);
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}
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}
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LangAS getCUDABuiltinAddressSpace(unsigned AS) const override {
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switch (AS) {
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case 0:
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return LangAS::Default;
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case 1:
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return LangAS::cuda_device;
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case 3:
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return LangAS::cuda_shared;
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case 4:
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return LangAS::cuda_constant;
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default:
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return getLangASFromTargetAS(AS);
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}
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}
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std::optional<LangAS> getConstantAddressSpace() const override {
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return getLangASFromTargetAS(llvm::AMDGPUAS::CONSTANT_ADDRESS);
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}
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const llvm::omp::GV &getGridValue() const override {
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switch (WavefrontSize) {
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case 32:
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return llvm::omp::getAMDGPUGridValues<32>();
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case 64:
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return llvm::omp::getAMDGPUGridValues<64>();
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default:
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llvm_unreachable("getGridValue not implemented for this wavesize");
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}
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}
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/// \returns Target specific vtbl ptr address space.
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unsigned getVtblPtrAddressSpace() const override {
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return static_cast<unsigned>(llvm::AMDGPUAS::CONSTANT_ADDRESS);
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}
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/// \returns If a target requires an address within a target specific address
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/// space \p AddressSpace to be converted in order to be used, then return the
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/// corresponding target specific DWARF address space.
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///
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/// \returns Otherwise return std::nullopt and no conversion will be emitted
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/// in the DWARF.
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std::optional<unsigned>
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getDWARFAddressSpace(unsigned AddressSpace) const override {
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const unsigned DWARF_Private = 1;
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const unsigned DWARF_Local = 2;
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if (AddressSpace == llvm::AMDGPUAS::PRIVATE_ADDRESS) {
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return DWARF_Private;
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} else if (AddressSpace == llvm::AMDGPUAS::LOCAL_ADDRESS) {
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return DWARF_Local;
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} else {
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return std::nullopt;
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}
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}
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CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
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switch (CC) {
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default:
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return CCCR_Warning;
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case CC_C:
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case CC_OpenCLKernel:
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case CC_AMDGPUKernelCall:
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return CCCR_OK;
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}
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}
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// In amdgcn target the null pointer in global, constant, and generic
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// address space has value 0 but in private and local address space has
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// value ~0.
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uint64_t getNullPointerValue(LangAS AS) const override {
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// FIXME: Also should handle region.
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return (AS == LangAS::opencl_local || AS == LangAS::opencl_private ||
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AS == LangAS::sycl_local || AS == LangAS::sycl_private)
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? ~0
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: 0;
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}
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void setAuxTarget(const TargetInfo *Aux) override;
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bool hasBitIntType() const override { return true; }
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// Record offload arch features since they are needed for defining the
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// pre-defined macros.
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override {
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auto TargetIDFeatures =
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getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind));
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for (const auto &F : Features) {
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assert(F.front() == '+' || F.front() == '-');
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if (F == "+wavefrontsize64")
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WavefrontSize = 64;
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else if (F == "+cumode")
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CUMode = true;
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else if (F == "-cumode")
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CUMode = false;
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else if (F == "+image-insts")
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HasImage = true;
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bool IsOn = F.front() == '+';
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StringRef Name = StringRef(F).drop_front();
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if (!llvm::is_contained(TargetIDFeatures, Name))
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continue;
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assert(!OffloadArchFeatures.contains(Name));
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OffloadArchFeatures[Name] = IsOn;
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}
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return true;
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}
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std::optional<std::string> getTargetID() const override {
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if (!isAMDGCN(getTriple()))
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return std::nullopt;
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// When -target-cpu is not set, we assume generic code that it is valid
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// for all GPU and use an empty string as target ID to represent that.
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if (GPUKind == llvm::AMDGPU::GK_NONE)
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return std::string("");
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return getCanonicalTargetID(getArchNameAMDGCN(GPUKind),
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OffloadArchFeatures);
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}
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bool hasHIPImageSupport() const override { return HasImage; }
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std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
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// This is imprecise as the value can vary between 64, 128 (even 256!) bytes
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// depending on the level of cache and the target architecture. We select
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// the size that corresponds to the largest L1 cache line for all
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// architectures.
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return std::make_pair(128, 128);
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}
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
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