ca79ff07d8
Reverts llvm/llvm-project#118734 There are currently some specific versions of MSVC that are miscompiling this code (we think). We don't know why as all the other build bots and at least some folks' local Windows builds work fine. This is a candidate revert to help the relevant folks catch their builders up and have time to debug the issue. However, the expectation is to roll forward at some point with a workaround if at all possible.
348 lines
12 KiB
C++
348 lines
12 KiB
C++
//===--- LoongArch.cpp - Implement LoongArch target feature support -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements LoongArch TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArch.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/LoongArchTargetParser.h"
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using namespace clang;
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using namespace clang::targets;
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ArrayRef<const char *> LoongArchTargetInfo::getGCCRegNames() const {
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static const char *const GCCRegNames[] = {
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// General purpose registers.
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"$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", "$r8", "$r9",
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"$r10", "$r11", "$r12", "$r13", "$r14", "$r15", "$r16", "$r17", "$r18",
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"$r19", "$r20", "$r21", "$r22", "$r23", "$r24", "$r25", "$r26", "$r27",
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"$r28", "$r29", "$r30", "$r31",
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// Floating point registers.
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"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
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"$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
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"$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
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"$f28", "$f29", "$f30", "$f31",
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// Condition flag registers.
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"$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7",
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// 128-bit vector registers.
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"$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6", "$vr7", "$vr8",
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"$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14", "$vr15", "$vr16",
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"$vr17", "$vr18", "$vr19", "$vr20", "$vr21", "$vr22", "$vr23", "$vr24",
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"$vr25", "$vr26", "$vr27", "$vr28", "$vr29", "$vr30", "$vr31",
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// 256-bit vector registers.
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"$xr0", "$xr1", "$xr2", "$xr3", "$xr4", "$xr5", "$xr6", "$xr7", "$xr8",
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"$xr9", "$xr10", "$xr11", "$xr12", "$xr13", "$xr14", "$xr15", "$xr16",
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"$xr17", "$xr18", "$xr19", "$xr20", "$xr21", "$xr22", "$xr23", "$xr24",
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"$xr25", "$xr26", "$xr27", "$xr28", "$xr29", "$xr30", "$xr31"};
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return llvm::ArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::GCCRegAlias>
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LoongArchTargetInfo::getGCCRegAliases() const {
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static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
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{{"zero", "$zero", "r0"}, "$r0"},
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{{"ra", "$ra", "r1"}, "$r1"},
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{{"tp", "$tp", "r2"}, "$r2"},
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{{"sp", "$sp", "r3"}, "$r3"},
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{{"a0", "$a0", "r4"}, "$r4"},
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{{"a1", "$a1", "r5"}, "$r5"},
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{{"a2", "$a2", "r6"}, "$r6"},
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{{"a3", "$a3", "r7"}, "$r7"},
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{{"a4", "$a4", "r8"}, "$r8"},
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{{"a5", "$a5", "r9"}, "$r9"},
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{{"a6", "$a6", "r10"}, "$r10"},
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{{"a7", "$a7", "r11"}, "$r11"},
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{{"t0", "$t0", "r12"}, "$r12"},
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{{"t1", "$t1", "r13"}, "$r13"},
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{{"t2", "$t2", "r14"}, "$r14"},
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{{"t3", "$t3", "r15"}, "$r15"},
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{{"t4", "$t4", "r16"}, "$r16"},
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{{"t5", "$t5", "r17"}, "$r17"},
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{{"t6", "$t6", "r18"}, "$r18"},
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{{"t7", "$t7", "r19"}, "$r19"},
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{{"t8", "$t8", "r20"}, "$r20"},
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{{"r21"}, "$r21"},
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{{"s9", "$s9", "r22", "fp", "$fp"}, "$r22"},
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{{"s0", "$s0", "r23"}, "$r23"},
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{{"s1", "$s1", "r24"}, "$r24"},
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{{"s2", "$s2", "r25"}, "$r25"},
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{{"s3", "$s3", "r26"}, "$r26"},
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{{"s4", "$s4", "r27"}, "$r27"},
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{{"s5", "$s5", "r28"}, "$r28"},
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{{"s6", "$s6", "r29"}, "$r29"},
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{{"s7", "$s7", "r30"}, "$r30"},
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{{"s8", "$s8", "r31"}, "$r31"},
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{{"$fa0"}, "$f0"},
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{{"$fa1"}, "$f1"},
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{{"$fa2"}, "$f2"},
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{{"$fa3"}, "$f3"},
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{{"$fa4"}, "$f4"},
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{{"$fa5"}, "$f5"},
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{{"$fa6"}, "$f6"},
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{{"$fa7"}, "$f7"},
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{{"$ft0"}, "$f8"},
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{{"$ft1"}, "$f9"},
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{{"$ft2"}, "$f10"},
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{{"$ft3"}, "$f11"},
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{{"$ft4"}, "$f12"},
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{{"$ft5"}, "$f13"},
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{{"$ft6"}, "$f14"},
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{{"$ft7"}, "$f15"},
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{{"$ft8"}, "$f16"},
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{{"$ft9"}, "$f17"},
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{{"$ft10"}, "$f18"},
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{{"$ft11"}, "$f19"},
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{{"$ft12"}, "$f20"},
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{{"$ft13"}, "$f21"},
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{{"$ft14"}, "$f22"},
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{{"$ft15"}, "$f23"},
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{{"$fs0"}, "$f24"},
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{{"$fs1"}, "$f25"},
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{{"$fs2"}, "$f26"},
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{{"$fs3"}, "$f27"},
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{{"$fs4"}, "$f28"},
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{{"$fs5"}, "$f29"},
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{{"$fs6"}, "$f30"},
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{{"$fs7"}, "$f31"},
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};
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return llvm::ArrayRef(GCCRegAliases);
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}
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bool LoongArchTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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// See the GCC definitions here:
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// https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
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// Note that the 'm' constraint is handled in TargetInfo.
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switch (*Name) {
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default:
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return false;
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case 'f':
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// A floating-point register (if available).
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Info.setAllowsRegister();
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return true;
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case 'k':
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// A memory operand whose address is formed by a base register and
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// (optionally scaled) index register.
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Info.setAllowsMemory();
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return true;
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case 'l':
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// A signed 16-bit constant.
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Info.setRequiresImmediate(-32768, 32767);
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return true;
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case 'I':
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// A signed 12-bit constant (for arithmetic instructions).
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Info.setRequiresImmediate(-2048, 2047);
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return true;
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case 'J':
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// Integer zero.
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Info.setRequiresImmediate(0);
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return true;
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case 'K':
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// An unsigned 12-bit constant (for logic instructions).
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Info.setRequiresImmediate(0, 4095);
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return true;
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case 'Z':
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// ZB: An address that is held in a general-purpose register. The offset is
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// zero.
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// ZC: A memory operand whose address is formed by a base register
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// and offset that is suitable for use in instructions with the same
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// addressing mode as ll.w and sc.w.
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if (Name[1] == 'C' || Name[1] == 'B') {
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Info.setAllowsMemory();
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++Name; // Skip over 'Z'.
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return true;
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}
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return false;
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}
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}
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std::string
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LoongArchTargetInfo::convertConstraint(const char *&Constraint) const {
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std::string R;
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switch (*Constraint) {
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case 'Z':
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// "ZC"/"ZB" are two-character constraints; add "^" hint for later
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// parsing.
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R = "^" + std::string(Constraint, 2);
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++Constraint;
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break;
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default:
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R = TargetInfo::convertConstraint(Constraint);
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break;
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}
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return R;
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}
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void LoongArchTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__loongarch__");
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unsigned GRLen = getRegisterWidth();
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Builder.defineMacro("__loongarch_grlen", Twine(GRLen));
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if (GRLen == 64)
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Builder.defineMacro("__loongarch64");
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if (HasFeatureD)
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Builder.defineMacro("__loongarch_frlen", "64");
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else if (HasFeatureF)
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Builder.defineMacro("__loongarch_frlen", "32");
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else
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Builder.defineMacro("__loongarch_frlen", "0");
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// Define __loongarch_arch.
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StringRef ArchName = getCPU();
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if (ArchName == "loongarch64") {
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if (HasFeatureLSX) {
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// TODO: As more features of the V1.1 ISA are supported, a unified "v1.1"
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// arch feature set will be used to include all sub-features belonging to
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// the V1.1 ISA version.
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if (HasFeatureFrecipe && HasFeatureLAM_BH && HasFeatureLAMCAS &&
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HasFeatureLD_SEQ_SA && HasFeatureDiv32)
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Builder.defineMacro("__loongarch_arch",
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Twine('"') + "la64v1.1" + Twine('"'));
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else
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Builder.defineMacro("__loongarch_arch",
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Twine('"') + "la64v1.0" + Twine('"'));
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} else {
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Builder.defineMacro("__loongarch_arch",
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Twine('"') + ArchName + Twine('"'));
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}
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} else {
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Builder.defineMacro("__loongarch_arch", Twine('"') + ArchName + Twine('"'));
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}
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// Define __loongarch_tune.
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StringRef TuneCPU = getTargetOpts().TuneCPU;
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if (TuneCPU.empty())
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TuneCPU = ArchName;
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Builder.defineMacro("__loongarch_tune", Twine('"') + TuneCPU + Twine('"'));
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if (HasFeatureLASX) {
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Builder.defineMacro("__loongarch_simd_width", "256");
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Builder.defineMacro("__loongarch_sx", Twine(1));
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Builder.defineMacro("__loongarch_asx", Twine(1));
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} else if (HasFeatureLSX) {
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Builder.defineMacro("__loongarch_simd_width", "128");
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Builder.defineMacro("__loongarch_sx", Twine(1));
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}
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if (HasFeatureFrecipe)
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Builder.defineMacro("__loongarch_frecipe", Twine(1));
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if (HasFeatureLAM_BH)
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Builder.defineMacro("__loongarch_lam_bh", Twine(1));
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if (HasFeatureLAMCAS)
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Builder.defineMacro("__loongarch_lamcas", Twine(1));
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if (HasFeatureLD_SEQ_SA)
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Builder.defineMacro("__loongarch_ld_seq_sa", Twine(1));
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if (HasFeatureDiv32)
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Builder.defineMacro("__loongarch_div32", Twine(1));
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StringRef ABI = getABI();
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if (ABI == "lp64d" || ABI == "lp64f" || ABI == "lp64s")
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Builder.defineMacro("__loongarch_lp64");
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if (ABI == "lp64d" || ABI == "ilp32d") {
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Builder.defineMacro("__loongarch_hard_float");
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Builder.defineMacro("__loongarch_double_float");
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} else if (ABI == "lp64f" || ABI == "ilp32f") {
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Builder.defineMacro("__loongarch_hard_float");
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Builder.defineMacro("__loongarch_single_float");
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} else if (ABI == "lp64s" || ABI == "ilp32s") {
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Builder.defineMacro("__loongarch_soft_float");
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}
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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if (GRLen == 64)
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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}
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static constexpr Builtin::Info BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#include "clang/Basic/BuiltinsLoongArch.def"
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};
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bool LoongArchTargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
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if (getTriple().getArch() == llvm::Triple::loongarch64)
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Features["64bit"] = true;
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if (getTriple().getArch() == llvm::Triple::loongarch32)
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Features["32bit"] = true;
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return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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}
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/// Return true if has this feature.
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bool LoongArchTargetInfo::hasFeature(StringRef Feature) const {
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bool Is64Bit = getTriple().getArch() == llvm::Triple::loongarch64;
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// TODO: Handle more features.
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return llvm::StringSwitch<bool>(Feature)
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.Case("loongarch32", !Is64Bit)
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.Case("loongarch64", Is64Bit)
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.Case("32bit", !Is64Bit)
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.Case("64bit", Is64Bit)
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.Case("lsx", HasFeatureLSX)
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.Case("lasx", HasFeatureLASX)
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.Default(false);
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}
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ArrayRef<Builtin::Info> LoongArchTargetInfo::getTargetBuiltins() const {
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return llvm::ArrayRef(BuiltinInfo, clang::LoongArch::LastTSBuiltin -
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Builtin::FirstTSBuiltin);
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}
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bool LoongArchTargetInfo::handleTargetFeatures(
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std::vector<std::string> &Features, DiagnosticsEngine &Diags) {
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for (const auto &Feature : Features) {
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if (Feature == "+d" || Feature == "+f") {
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// "d" implies "f".
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HasFeatureF = true;
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if (Feature == "+d") {
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HasFeatureD = true;
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}
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} else if (Feature == "+lsx")
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HasFeatureLSX = true;
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else if (Feature == "+lasx")
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HasFeatureLASX = true;
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else if (Feature == "-ual")
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HasUnalignedAccess = false;
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else if (Feature == "+frecipe")
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HasFeatureFrecipe = true;
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else if (Feature == "+lam-bh")
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HasFeatureLAM_BH = true;
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else if (Feature == "+lamcas")
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HasFeatureLAMCAS = true;
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else if (Feature == "+ld-seq-sa")
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HasFeatureLD_SEQ_SA = true;
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else if (Feature == "+div32")
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HasFeatureDiv32 = true;
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}
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return true;
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}
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bool LoongArchTargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::LoongArch::isValidCPUName(Name);
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}
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void LoongArchTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::LoongArch::fillValidCPUList(Values);
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}
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