ca79ff07d8
Reverts llvm/llvm-project#118734 There are currently some specific versions of MSVC that are miscompiling this code (we think). We don't know why as all the other build bots and at least some folks' local Windows builds work fine. This is a candidate revert to help the relevant folks catch their builders up and have time to debug the issue. However, the expectation is to roll forward at some point with a workaround if at all possible.
554 lines
20 KiB
C++
554 lines
20 KiB
C++
//===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares PPC TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
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#include "OSTargets.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/TargetParser/Triple.h"
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namespace clang {
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namespace targets {
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// PPC abstract base class
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class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
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/// Flags for architecture specific defines.
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typedef enum {
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ArchDefineNone = 0,
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ArchDefineName = 1 << 0, // <name> is substituted for arch name.
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ArchDefinePpcgr = 1 << 1,
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ArchDefinePpcsq = 1 << 2,
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ArchDefine440 = 1 << 3,
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ArchDefine603 = 1 << 4,
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ArchDefine604 = 1 << 5,
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ArchDefinePwr4 = 1 << 6,
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ArchDefinePwr5 = 1 << 7,
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ArchDefinePwr5x = 1 << 8,
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ArchDefinePwr6 = 1 << 9,
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ArchDefinePwr6x = 1 << 10,
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ArchDefinePwr7 = 1 << 11,
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ArchDefinePwr8 = 1 << 12,
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ArchDefinePwr9 = 1 << 13,
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ArchDefinePwr10 = 1 << 14,
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ArchDefinePwr11 = 1 << 15,
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ArchDefineFuture = 1 << 16,
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ArchDefineA2 = 1 << 17,
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ArchDefineE500 = 1 << 18
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} ArchDefineTypes;
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ArchDefineTypes ArchDefs = ArchDefineNone;
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static const char *const GCCRegNames[];
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static const TargetInfo::GCCRegAlias GCCRegAliases[];
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std::string CPU;
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enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
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// Target cpu features.
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bool HasAltivec = false;
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bool HasMMA = false;
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bool HasROPProtect = false;
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bool HasPrivileged = false;
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bool HasAIXSmallLocalExecTLS = false;
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bool HasAIXSmallLocalDynamicTLS = false;
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bool HasVSX = false;
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bool UseCRBits = false;
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bool HasP8Vector = false;
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bool HasP8Crypto = false;
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bool HasDirectMove = false;
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bool HasHTM = false;
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bool HasBPERMD = false;
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bool HasExtDiv = false;
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bool HasP9Vector = false;
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bool HasSPE = false;
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bool HasFrsqrte = false;
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bool HasFrsqrtes = false;
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bool PairedVectorMemops = false;
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bool HasP10Vector = false;
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bool HasPCRelativeMemops = false;
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bool HasPrefixInstrs = false;
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bool IsISA2_06 = false;
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bool IsISA2_07 = false;
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bool IsISA3_0 = false;
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bool IsISA3_1 = false;
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bool HasQuadwordAtomics = false;
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bool HasAIXShLibTLSModelOpt = false;
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bool UseLongCalls = false;
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protected:
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std::string ABI;
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public:
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PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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: TargetInfo(Triple) {
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SuitableAlign = 128;
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LongDoubleWidth = LongDoubleAlign = 128;
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LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
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HasStrictFP = true;
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HasIbm128 = true;
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HasUnalignedAccess = true;
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}
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// Set the language option for altivec based on our value.
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void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
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// Note: GCC recognizes the following additional cpus:
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// 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
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// 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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bool CPUKnown = isValidCPUName(Name);
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if (CPUKnown) {
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CPU = Name;
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// CPU identification.
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ArchDefs =
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(ArchDefineTypes)llvm::StringSwitch<int>(CPU)
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.Case("440", ArchDefineName)
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.Case("450", ArchDefineName | ArchDefine440)
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.Case("601", ArchDefineName)
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.Case("602", ArchDefineName | ArchDefinePpcgr)
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.Case("603", ArchDefineName | ArchDefinePpcgr)
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.Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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.Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
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.Case("604", ArchDefineName | ArchDefinePpcgr)
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.Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
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.Case("620", ArchDefineName | ArchDefinePpcgr)
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.Case("630", ArchDefineName | ArchDefinePpcgr)
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.Case("7400", ArchDefineName | ArchDefinePpcgr)
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.Case("7450", ArchDefineName | ArchDefinePpcgr)
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.Case("750", ArchDefineName | ArchDefinePpcgr)
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.Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
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ArchDefinePpcsq)
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.Case("a2", ArchDefineA2)
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.Cases("power3", "pwr3", ArchDefinePpcgr)
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.Cases("power4", "pwr4",
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ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("power5", "pwr5",
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ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
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ArchDefinePpcsq)
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.Cases("power5x", "pwr5x",
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ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
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ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("power6", "pwr6",
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ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
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ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("power6x", "pwr6x",
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ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
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ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
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ArchDefinePpcsq)
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.Cases("power7", "pwr7",
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ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
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ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
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ArchDefinePpcsq)
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// powerpc64le automatically defaults to at least power8.
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.Cases("power8", "pwr8", "ppc64le",
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ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
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ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
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ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("power9", "pwr9",
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ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
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ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
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ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("power10", "pwr10",
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ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
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ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
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ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
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ArchDefinePpcsq)
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.Cases("power11", "pwr11",
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ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 |
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ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
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ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
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ArchDefinePpcgr | ArchDefinePpcsq)
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.Case("future",
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ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 |
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ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
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ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
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ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
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.Cases("8548", "e500", ArchDefineE500)
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.Default(ArchDefineNone);
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}
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return CPUKnown;
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}
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StringRef getABI() const override { return ABI; }
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ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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bool isCLZForZeroUndef() const override { return false; }
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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bool
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initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const override;
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void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
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void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const;
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void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override;
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bool hasFeature(StringRef Feature) const override;
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void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
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bool Enabled) const override;
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bool supportsTargetAttributeTune() const override { return true; }
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ArrayRef<const char *> getGCCRegNames() const override;
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
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ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &Info) const override {
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switch (*Name) {
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default:
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return false;
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case 'O': // Zero
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break;
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case 'f': // Floating point register
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// Don't use floating point registers on soft float ABI.
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if (FloatABI == SoftFloat)
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return false;
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[[fallthrough]];
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case 'b': // Base register
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Info.setAllowsRegister();
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break;
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// FIXME: The following are added to allow parsing.
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// I just took a guess at what the actions should be.
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// Also, is more specific checking needed? I.e. specific registers?
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case 'd': // Floating point register (containing 64-bit value)
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case 'v': // Altivec vector register
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// Don't use floating point and altivec vector registers
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// on soft float ABI
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if (FloatABI == SoftFloat)
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return false;
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Info.setAllowsRegister();
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break;
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case 'w':
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switch (Name[1]) {
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case 'd': // VSX vector register to hold vector double data
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case 'f': // VSX vector register to hold vector float data
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case 's': // VSX vector register to hold scalar double data
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case 'w': // VSX vector register to hold scalar double data
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case 'a': // Any VSX register
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case 'c': // An individual CR bit
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case 'i': // FP or VSX register to hold 64-bit integers data
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break;
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default:
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return false;
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}
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Info.setAllowsRegister();
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Name++; // Skip over 'w'.
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break;
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case 'h': // `MQ', `CTR', or `LINK' register
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case 'q': // `MQ' register
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case 'c': // `CTR' register
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case 'l': // `LINK' register
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case 'x': // `CR' register (condition register) number 0
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case 'y': // `CR' register (condition register)
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case 'z': // `XER[CA]' carry bit (part of the XER register)
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Info.setAllowsRegister();
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break;
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case 'I': // Signed 16-bit constant
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case 'J': // Unsigned 16-bit constant shifted left 16 bits
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// (use `L' instead for SImode constants)
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case 'K': // Unsigned 16-bit constant
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case 'L': // Signed 16-bit constant shifted left 16 bits
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case 'M': // Constant larger than 31
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case 'N': // Exact power of 2
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case 'P': // Constant whose negation is a signed 16-bit constant
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case 'G': // Floating point constant that can be loaded into a
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// register with one instruction per word
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case 'H': // Integer/Floating point constant that can be loaded
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// into a register using three instructions
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break;
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case 'm': // Memory operand. Note that on PowerPC targets, m can
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// include addresses that update the base register. It
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// is therefore only safe to use `m' in an asm statement
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// if that asm statement accesses the operand exactly once.
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// The asm statement must also use `%U<opno>' as a
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// placeholder for the "update" flag in the corresponding
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// load or store instruction. For example:
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// asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
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// is correct but:
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// asm ("st %1,%0" : "=m" (mem) : "r" (val));
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// is not. Use es rather than m if you don't want the base
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// register to be updated.
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case 'e':
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if (Name[1] != 's')
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return false;
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// es: A "stable" memory operand; that is, one which does not
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// include any automodification of the base register. Unlike
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// `m', this constraint can be used in asm statements that
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// might access the operand several times, or that might not
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// access it at all.
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Info.setAllowsMemory();
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Name++; // Skip over 'e'.
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break;
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case 'Q': // Memory operand that is an offset from a register (it is
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// usually better to use `m' or `es' in asm statements)
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Info.setAllowsRegister();
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[[fallthrough]];
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case 'Z': // Memory operand that is an indexed or indirect from a
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// register (it is usually better to use `m' or `es' in
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// asm statements)
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Info.setAllowsMemory();
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break;
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case 'a': // Address operand that is an indexed or indirect from a
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// register (`p' is preferable for asm statements)
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// TODO: Add full support for this constraint
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return false;
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case 'R': // AIX TOC entry
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case 'S': // Constant suitable as a 64-bit mask operand
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case 'T': // Constant suitable as a 32-bit mask operand
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case 'U': // System V Release 4 small data area reference
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case 't': // AND masks that can be performed by two rldic{l, r}
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// instructions
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case 'W': // Vector constant that does not require memory
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case 'j': // Vector constant that is all zeros.
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break;
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// End FIXME.
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}
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return true;
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}
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std::string convertConstraint(const char *&Constraint) const override {
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std::string R;
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switch (*Constraint) {
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case 'e':
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case 'w':
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// Two-character constraint; add "^" hint for later parsing.
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R = std::string("^") + std::string(Constraint, 2);
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Constraint++;
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break;
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default:
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return TargetInfo::convertConstraint(Constraint);
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}
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return R;
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}
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std::string_view getClobbers() const override { return ""; }
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int getEHDataRegisterNumber(unsigned RegNo) const override {
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if (RegNo == 0)
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return 3;
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if (RegNo == 1)
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return 4;
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return -1;
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}
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bool hasSjLjLowering() const override { return true; }
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const char *getLongDoubleMangling() const override {
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if (LongDoubleWidth == 64)
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return "e";
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return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
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? "g"
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: "u9__ieee128";
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}
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const char *getFloat128Mangling() const override { return "u9__ieee128"; }
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const char *getIbm128Mangling() const override { return "g"; }
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bool hasBitIntType() const override { return true; }
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bool isSPRegName(StringRef RegName) const override {
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return RegName == "r1" || RegName == "x1";
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}
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// We support __builtin_cpu_supports/__builtin_cpu_is on targets that
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// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
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static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
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static constexpr int MINIMUM_AIX_OS_MINOR = 2;
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bool supportsCpuSupports() const override {
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llvm::Triple Triple = getTriple();
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// AIX 7.2 is the minimum requirement to support __builtin_cpu_supports().
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return Triple.isOSGlibc() ||
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(Triple.isOSAIX() &&
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!Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR));
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}
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bool supportsCpuIs() const override {
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llvm::Triple Triple = getTriple();
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// AIX 7.2 is the minimum requirement to support __builtin_cpu_is().
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return Triple.isOSGlibc() ||
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(Triple.isOSAIX() &&
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!Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR));
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}
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bool validateCpuSupports(StringRef Feature) const override;
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bool validateCpuIs(StringRef Name) const override;
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};
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class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
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public:
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PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: PPCTargetInfo(Triple, Opts) {
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if (Triple.isOSAIX())
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resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
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else if (Triple.getArch() == llvm::Triple::ppcle)
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resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
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else
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resetDataLayout("E-m:e-p:32:32-Fn32-i64:64-n32");
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switch (getTriple().getOS()) {
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case llvm::Triple::Linux:
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case llvm::Triple::FreeBSD:
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case llvm::Triple::NetBSD:
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SizeType = UnsignedInt;
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PtrDiffType = SignedInt;
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IntPtrType = SignedInt;
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break;
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case llvm::Triple::AIX:
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SizeType = UnsignedLong;
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PtrDiffType = SignedLong;
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IntPtrType = SignedLong;
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LongDoubleWidth = 64;
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LongDoubleAlign = DoubleAlign = 32;
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LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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break;
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default:
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break;
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}
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if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
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Triple.isMusl()) {
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LongDoubleWidth = LongDoubleAlign = 64;
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LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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}
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// PPC32 supports atomics up to 4 bytes.
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
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}
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BuiltinVaListKind getBuiltinVaListKind() const override {
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// This is the ELF definition
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return TargetInfo::PowerABIBuiltinVaList;
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}
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std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
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return std::make_pair(32, 32);
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}
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};
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// Note: ABI differences may eventually require us to have a separate
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// TargetInfo for little endian.
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class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
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public:
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PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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|
: PPCTargetInfo(Triple, Opts) {
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|
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
|
|
IntMaxType = SignedLong;
|
|
Int64Type = SignedLong;
|
|
std::string DataLayout;
|
|
|
|
if (Triple.isOSAIX()) {
|
|
// TODO: Set appropriate ABI for AIX platform.
|
|
DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64";
|
|
LongDoubleWidth = 64;
|
|
LongDoubleAlign = DoubleAlign = 32;
|
|
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
|
|
} else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
|
|
DataLayout = "e-m:e-Fn32-i64:64-i128:128-n32:64";
|
|
ABI = "elfv2";
|
|
} else {
|
|
DataLayout = "E-m:e";
|
|
if (Triple.isPPC64ELFv2ABI()) {
|
|
ABI = "elfv2";
|
|
DataLayout += "-Fn32";
|
|
} else {
|
|
ABI = "elfv1";
|
|
DataLayout += "-Fi64";
|
|
}
|
|
DataLayout += "-i64:64-i128:128-n32:64";
|
|
}
|
|
|
|
if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
|
|
LongDoubleWidth = LongDoubleAlign = 64;
|
|
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
|
|
}
|
|
|
|
if (Triple.isOSAIX() || Triple.isOSLinux())
|
|
DataLayout += "-S128-v256:256:256-v512:512:512";
|
|
resetDataLayout(DataLayout);
|
|
|
|
// Newer PPC64 instruction sets support atomics up to 16 bytes.
|
|
MaxAtomicPromoteWidth = 128;
|
|
// Baseline PPC64 supports inlining atomics up to 8 bytes.
|
|
MaxAtomicInlineWidth = 64;
|
|
}
|
|
|
|
void setMaxAtomicWidth() override {
|
|
// For power8 and up, backend is able to inline 16-byte atomic lock free
|
|
// code.
|
|
// TODO: We should allow AIX to inline quadword atomics in the future.
|
|
if (!getTriple().isOSAIX() && hasFeature("quadword-atomics"))
|
|
MaxAtomicInlineWidth = 128;
|
|
}
|
|
|
|
BuiltinVaListKind getBuiltinVaListKind() const override {
|
|
return TargetInfo::CharPtrBuiltinVaList;
|
|
}
|
|
|
|
// PPC64 Linux-specific ABI options.
|
|
bool setABI(const std::string &Name) override {
|
|
if (Name == "elfv1" || Name == "elfv2") {
|
|
ABI = Name;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
|
|
switch (CC) {
|
|
case CC_Swift:
|
|
return CCCR_OK;
|
|
case CC_SwiftAsync:
|
|
return CCCR_Error;
|
|
default:
|
|
return CCCR_Warning;
|
|
}
|
|
}
|
|
|
|
std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
|
|
return std::make_pair(128, 128);
|
|
}
|
|
};
|
|
|
|
class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
|
|
public AIXTargetInfo<PPC32TargetInfo> {
|
|
public:
|
|
using AIXTargetInfo::AIXTargetInfo;
|
|
BuiltinVaListKind getBuiltinVaListKind() const override {
|
|
return TargetInfo::CharPtrBuiltinVaList;
|
|
}
|
|
};
|
|
|
|
class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
|
|
public AIXTargetInfo<PPC64TargetInfo> {
|
|
public:
|
|
using AIXTargetInfo::AIXTargetInfo;
|
|
};
|
|
|
|
} // namespace targets
|
|
} // namespace clang
|
|
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
|