db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
158 lines
3.8 KiB
LLVM
158 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -o - -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,GISEL
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; RUN: llc < %s -o - -verify-machineinstrs -global-isel=0 | FileCheck %s --check-prefixes=CHECK,SDAG
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios14.5.0"
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define i32 @bfi_w_31(i32 %in1, i32 %in2) {
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; CHECK-LABEL: bfi_w_31:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi w1, w0, #31, #1
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i32 %in1, 31
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%tmp4 = and i32 %in2, 2147483647
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%out = or i32 %tmp3, %tmp4
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ret i32 %out
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}
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define i32 @bfi_w_8(i32 %in1, i32 %in2) {
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; CHECK-LABEL: bfi_w_8:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi w1, w0, #8, #24
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i32 %in1, 8
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%tmp4 = and i32 %in2, 255
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%out = or i32 %tmp3, %tmp4
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ret i32 %out
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}
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define i32 @bfi_w_1(i32 %in1, i32 %in2) {
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; CHECK-LABEL: bfi_w_1:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi w1, w0, #1, #31
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; CHECK-NEXT: mov w0, w1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i32 %in1, 1
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%tmp4 = and i32 %in2, 1
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%out = or i32 %tmp3, %tmp4
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ret i32 %out
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}
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define i64 @bfi_x_63(i64 %in1, i64 %in2) {
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; CHECK-LABEL: bfi_x_63:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi x1, x0, #63, #1
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 63
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%tmp4 = and i64 %in2, 9223372036854775807
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%out = or i64 %tmp3, %tmp4
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ret i64 %out
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}
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define i64 @bfi_x_31(i64 %in1, i64 %in2) {
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; CHECK-LABEL: bfi_x_31:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi x1, x0, #31, #33
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 31
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%tmp4 = and i64 %in2, 2147483647
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%out = or i64 %tmp3, %tmp4
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ret i64 %out
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}
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define i64 @bfi_x_8(i64 %in1, i64 %in2) {
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; CHECK-LABEL: bfi_x_8:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi x1, x0, #8, #56
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 8
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%tmp4 = and i64 %in2, 255
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%out = or i64 %tmp3, %tmp4
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ret i64 %out
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}
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define i64 @bfi_x_1(i64 %in1, i64 %in2) {
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; CHECK-LABEL: bfi_x_1:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi x1, x0, #1, #63
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 1
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%tmp4 = and i64 %in2, 1
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%out = or i64 %tmp3, %tmp4
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ret i64 %out
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}
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define i64 @bfi_x_1_swapped(i64 %in1, i64 %in2) {
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; CHECK-LABEL: bfi_x_1_swapped:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: bfi x1, x0, #1, #63
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 1
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%tmp4 = and i64 %in2, 1
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%out = or i64 %tmp4, %tmp3
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ret i64 %out
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}
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define i64 @extra_use1(i64 %in1, i64 %in2, ptr %p) {
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; GISEL-LABEL: extra_use1:
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; GISEL: ; %bb.0: ; %bb
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; GISEL-NEXT: lsl x8, x0, #1
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; GISEL-NEXT: and x9, x1, #0x1
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; GISEL-NEXT: orr x0, x8, x9
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; GISEL-NEXT: str x8, [x2]
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; GISEL-NEXT: ret
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;
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; SDAG-LABEL: extra_use1:
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; SDAG: ; %bb.0: ; %bb
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; SDAG-NEXT: bfi x1, x0, #1, #63
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; SDAG-NEXT: lsl x8, x0, #1
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; SDAG-NEXT: mov x0, x1
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; SDAG-NEXT: str x8, [x2]
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; SDAG-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 1
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%tmp4 = and i64 %in2, 1
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%out = or i64 %tmp3, %tmp4
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store i64 %tmp3, ptr %p
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ret i64 %out
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}
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define i64 @extra_use2(i64 %in1, i64 %in2, ptr %p) {
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; GISEL-LABEL: extra_use2:
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; GISEL: ; %bb.0: ; %bb
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; GISEL-NEXT: and x8, x1, #0x1
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; GISEL-NEXT: orr x0, x8, x0, lsl #1
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; GISEL-NEXT: str x8, [x2]
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; GISEL-NEXT: ret
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;
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; SDAG-LABEL: extra_use2:
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; SDAG: ; %bb.0: ; %bb
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; SDAG-NEXT: and x8, x1, #0x1
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; SDAG-NEXT: bfi x1, x0, #1, #63
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; SDAG-NEXT: str x8, [x2]
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; SDAG-NEXT: mov x0, x1
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; SDAG-NEXT: ret
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bb:
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%tmp3 = shl i64 %in1, 1
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%tmp4 = and i64 %in2, 1
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%out = or i64 %tmp3, %tmp4
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store i64 %tmp4, ptr %p
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ret i64 %out
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}
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