a0c318938a
Both are based on MachineLICMBase, and the functionality there is "switched" based on a PreRegAlloc flag. This commit is simply about trusting the original value of that flag, defined by the `MachineLICM` and `EarlyMachineLICM` classes. The `PreRegAlloc` flag used to be overwritten it based on MRI.isSSA(), which is un-reliable due to how it is inferred by the MIRParser. I see that we can now define isSSA in MIR (thanks @gargaroff ), meaning the fix isn’t really needed anymore, but redefining that flag still feels wrong. Note that I'm looking into upstreaming more changes to MachineLICM, see [the discourse thread](https://discourse.llvm.org/t/extending-post-regalloc-machinelicm/82725).
60 lines
1.4 KiB
YAML
60 lines
1.4 KiB
YAML
# RUN: llc -mtriple=aarch64 -run-pass machinelicm -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -mtriple=aarch64 -passes machinelicm -o - %s | FileCheck %s
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---
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name: test
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 8, type: spill-slot }
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body: |
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bb.0:
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; CHECK-LABEL: name: test
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; CHECK-LABEL: bb.0:
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; CHECK: $x2 = LDRXui %stack.0, 0
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liveins: $x0, $x1, $x2
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B %bb.1
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bb.1:
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; CHECK-LABEL: bb.1:
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; CHECK-NOT: $x2 = LDRXui %stack.0, 0
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; CHECK: $x0 = ADDXrr $x0, $x2
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liveins: $x0
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DBG_VALUE %stack.0, 0
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$x2 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
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$x0 = ADDXrr $x0, killed $x2
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$xzr = SUBSXri killed $x0, 1, 0, implicit-def $nzcv
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Bcc 11, %bb.1, implicit $nzcv
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B %bb.2
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bb.2:
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liveins: $x0
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...
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---
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name: test2
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 8, type: spill-slot }
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body: |
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bb.0:
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; CHECK-LABEL: name: test2
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; CHECK-LABEL: bb.0:
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; CHECK: $x2 = LDRXui %stack.0, 0
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liveins: $x0, $x1, $x2
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B %bb.1
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bb.1:
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; CHECK-LABEL: bb.1:
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; CHECK-NOT: $x2 = LDRXui %stack.0, 0
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; CHECK: $w0 = ADDWrr $w0, $w2
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liveins: $x0
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DBG_VALUE %stack.0, 0
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$x2 = LDRXui %stack.0, 0 :: (load (s64) from %stack.0)
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$w0 = ADDWrr $w0, killed $w2
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$wzr = SUBSWri killed $w0, 1, 0, implicit-def $nzcv
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Bcc 11, %bb.1, implicit $nzcv
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B %bb.2
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bb.2:
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liveins: $x0
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...
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