4cce10743d
Had been doing this piece by piece, but makes more sense to do it in a single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD` addressing modes for atomic operations, along with a variety of tests. The `CodeModel` tests have been rearranged, as some of the new addressing modes are only exercised under some combinations of `CodeModel` and relocation mode
42 lines
1.0 KiB
LLVM
42 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=m68k-linux-gnu --code-model=large < %s | FileCheck %s
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; RUN: llc -mtriple=m68k-linux-gnu --code-model=large --relocation-model=pic < %s | FileCheck %s --check-prefix=PIC
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; M68k's libgcc does NOT have __sync_synchronize so we shouldn't
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; lower to that.
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define void @atomic_fence() {
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; CHECK-LABEL: atomic_fence:
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; CHECK: .cfi_startproc
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; CHECK-NEXT: ; %bb.0: ; %entry
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; CHECK-NEXT: ;APP
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; CHECK-NEXT: ;NO_APP
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; CHECK-NEXT: ;APP
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; CHECK-NEXT: ;NO_APP
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; CHECK-NEXT: ;APP
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; CHECK-NEXT: ;NO_APP
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; CHECK-NEXT: ;APP
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; CHECK-NEXT: ;NO_APP
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; CHECK-NEXT: rts
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;
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; PIC-LABEL: atomic_fence:
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; PIC: .cfi_startproc
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; PIC-NEXT: ; %bb.0: ; %entry
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; PIC-NEXT: ;APP
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; PIC-NEXT: ;NO_APP
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; PIC-NEXT: ;APP
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; PIC-NEXT: ;NO_APP
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; PIC-NEXT: ;APP
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; PIC-NEXT: ;NO_APP
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; PIC-NEXT: ;APP
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; PIC-NEXT: ;NO_APP
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; PIC-NEXT: rts
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entry:
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fence acquire
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fence release
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fence acq_rel
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fence seq_cst
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ret void
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}
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