228f88fdc8
This change implements support for the `cr` and `cf` register constraints (which allocate a RVC GPR or RVC FPR respectively), and the `N` modifier (which prints the raw encoding of a register rather than the name). The intention behind these additions is to make it easier to use inline assembly when assembling raw instructions that are not supported by the compiler, for instance when experimenting with new instructions or when supporting proprietary extensions outside the toolchain. These implement part of my proposal in riscv-non-isa/riscv-c-api-doc#92 As part of the implementation, I felt there was not enough coverage of inline assembly and the "in X" floating-point extensions, so I have added more regression tests around these configurations.
65 lines
2.2 KiB
LLVM
65 lines
2.2 KiB
LLVM
; RUN: not llc -mtriple=riscv32 < %s 2>&1 | FileCheck %s
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; RUN: not llc -mtriple=riscv64 < %s 2>&1 | FileCheck %s
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define void @constraint_I() {
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; CHECK: error: value out of range for constraint 'I'
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tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2048)
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; CHECK: error: value out of range for constraint 'I'
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tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2049)
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ret void
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}
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define void @constraint_J() {
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; CHECK: error: value out of range for constraint 'J'
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tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 1)
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ret void
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}
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define void @constraint_K() {
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; CHECK: error: value out of range for constraint 'K'
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tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 32)
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; CHECK: error: value out of range for constraint 'K'
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tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 -1)
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ret void
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}
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define void @constraint_f() nounwind {
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; CHECK: error: couldn't allocate input reg for constraint 'f'
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tail call void asm "fadd.s fa0, fa0, $0", "f"(float 0.0)
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; CHECK: error: couldn't allocate input reg for constraint 'f'
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tail call void asm "fadd.d fa0, fa0, $0", "f"(double 0.0)
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ret void
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}
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define void @constraint_cf() nounwind {
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; CHECK: error: couldn't allocate input reg for constraint 'cf'
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tail call void asm "fadd.s fa0, fa0, $0", "^cf"(float 0.0)
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; CHECK: error: couldn't allocate input reg for constraint 'cf'
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tail call void asm "fadd.d fa0, fa0, $0", "^cf"(double 0.0)
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ret void
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}
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define void @constraint_r_fixed_vec() nounwind {
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; CHECK: error: couldn't allocate input reg for constraint 'r'
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tail call void asm "add a0, a0, $0", "r"(<4 x i32> zeroinitializer)
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ret void
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}
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define void @constraint_r_scalable_vec() nounwind {
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; CHECK: error: couldn't allocate input reg for constraint 'r'
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tail call void asm "add a0, a0, $0", "r"(<vscale x 4 x i32> zeroinitializer)
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ret void
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}
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define void @constraint_cr_fixed_vec() nounwind {
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; CHECK: error: couldn't allocate input reg for constraint 'cr'
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tail call void asm "add a0, a0, $0", "^cr"(<4 x i32> zeroinitializer)
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ret void
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}
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define void @constraint_cr_scalable_vec() nounwind {
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; CHECK: error: couldn't allocate input reg for constraint 'cr'
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tail call void asm "add a0, a0, $0", "^cr"(<vscale x 4 x i32> zeroinitializer)
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ret void
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}
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