67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
63 lines
2.3 KiB
LLVM
63 lines
2.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: OpName [[SCALARi32:%.+]] "select_i32"
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; CHECK-DAG: OpName [[SCALARPTR:%.+]] "select_ptr"
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; CHECK-DAG: OpName [[VEC2i32:%.+]] "select_i32v2"
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; CHECK-DAG: OpName [[VEC2i32v2:%.+]] "select_v2i32v2"
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; CHECK: [[SCALARi32]] = OpFunction
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; CHECK-NEXT: [[C:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[T:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[F:%.+]] = OpFunctionParameter
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; CHECK: OpLabel
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; CHECK: [[R:%.+]] = OpSelect {{%.+}} [[C]] [[T]] [[F]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define i32 @select_i32(i1 %c, i32 %t, i32 %f) {
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%r = select i1 %c, i32 %t, i32 %f
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ret i32 %r
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}
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; CHECK: [[SCALARPTR]] = OpFunction
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; CHECK-NEXT: [[C:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[T:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[F:%.+]] = OpFunctionParameter
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; CHECK: OpLabel
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; CHECK: [[R:%.+]] = OpSelect {{%.+}} [[C]] [[T]] [[F]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define ptr @select_ptr(i1 %c, ptr %t, ptr %f) {
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%r = select i1 %c, ptr %t, ptr %f
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ret ptr %r
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}
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; CHECK: [[VEC2i32]] = OpFunction
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; CHECK-NEXT: [[C:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[T:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[F:%.+]] = OpFunctionParameter
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; CHECK: OpLabel
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; CHECK: [[R:%.+]] = OpSelect {{%.+}} [[C]] [[T]] [[F]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i32> @select_i32v2(i1 %c, <2 x i32> %t, <2 x i32> %f) {
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%r = select i1 %c, <2 x i32> %t, <2 x i32> %f
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ret <2 x i32> %r
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}
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; CHECK: [[VEC2i32v2]] = OpFunction
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; CHECK-NEXT: [[C:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[T:%.+]] = OpFunctionParameter
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; CHECK-NEXT: [[F:%.+]] = OpFunctionParameter
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; CHECK: OpLabel
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; CHECK: [[R:%.+]] = OpSelect {{%.+}} [[C]] [[T]] [[F]]
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; CHECK: OpReturnValue [[R]]
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; CHECK-NEXT: OpFunctionEnd
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define <2 x i32> @select_v2i32v2(<2 x i1> %c, <2 x i32> %t, <2 x i32> %f) {
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%r = select <2 x i1> %c, <2 x i32> %t, <2 x i32> %f
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ret <2 x i32> %r
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}
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