3a5cf6d99b
Use uppercase in the subvector description ("32x2" -> "32X4" etc.) - matches what we already do in VBROADCAST??X?, and we try to use uppercase for all x86 instruction mnemonics anyway (and lowercase just for the arg description suffix).
145 lines
4.2 KiB
YAML
145 lines
4.2 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
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--- |
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define void @test_insert_128_idx0() {
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ret void
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}
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define void @test_insert_128_idx0_undef() {
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ret void
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}
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define void @test_insert_128_idx1() {
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ret void
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}
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define void @test_insert_128_idx1_undef() {
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ret void
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}
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...
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---
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name: test_insert_128_idx0
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# ALL-LABEL: name: test_insert_128_idx0
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0:vr256 = COPY $ymm0
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# AVX-NEXT: %1:vr128 = COPY $xmm1
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# AVX-NEXT: %2:vr256 = VINSERTF128rri %0, %1, 0
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# AVX-NEXT: $ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit $ymm0
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#
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# AVX512VL: %0:vr256x = COPY $ymm0
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# AVX512VL-NEXT: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 0
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# AVX512VL-NEXT: $ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit $ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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%0(<8 x s32>) = COPY $ymm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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$ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_128_idx0_undef
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# ALL-LABEL: name: test_insert_128_idx0_undef
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %1:vr128 = COPY $xmm1
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# AVX-NEXT: undef %2.sub_xmm:vr256 = COPY %1
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# AVX-NEXT: $ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit $ymm0
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#
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# AVX512VL: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: undef %2.sub_xmm:vr256x = COPY %1
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# AVX512VL-NEXT: $ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit $ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY $xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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$ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_128_idx1
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# ALL-LABEL: name: test_insert_128_idx1
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0:vr256 = COPY $ymm0
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# AVX-NEXT: %1:vr128 = COPY $xmm1
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# AVX-NEXT: %2:vr256 = VINSERTF128rri %0, %1, 1
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# AVX-NEXT: $ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit $ymm0
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#
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# AVX512VL: %0:vr256x = COPY $ymm0
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# AVX512VL-NEXT: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 1
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# AVX512VL-NEXT: $ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit $ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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%0(<8 x s32>) = COPY $ymm0
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%1(<4 x s32>) = COPY $xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
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$ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit $ymm0
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...
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---
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name: test_insert_128_idx1_undef
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# ALL-LABEL: name: test_insert_128_idx1_undef
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0:vr256 = IMPLICIT_DEF
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# AVX-NEXT: %1:vr128 = COPY $xmm1
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# AVX-NEXT: %2:vr256 = VINSERTF128rri %0, %1, 1
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# AVX-NEXT: $ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit $ymm0
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#
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# AVX512VL: %0:vr256x = IMPLICIT_DEF
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# AVX512VL-NEXT: %1:vr128x = COPY $xmm1
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# AVX512VL-NEXT: %2:vr256x = VINSERTF32X4Z256rri %0, %1, 1
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# AVX512VL-NEXT: $ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit $ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: $ymm0, $ymm1
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY $xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
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$ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit $ymm0
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...
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