f6e1d64458
Enables interaleaved stores, results in better estimation for segmented stores for RISC-V Reviewers: preames, topperc, RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/115354
45 lines
2.0 KiB
LLVM
45 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux -mattr=+v -pass-remarks-output=%t -mcpu=sifive-p670 < %s | FileCheck %s
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; RUN: FileCheck %s --check-prefix YAML --input-file=%t
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; YAML-LABEL: --- !Passed
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; YAML-NEXT: Pass: slp-vectorizer
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; YAML-NEXT: Name: StoresVectorized
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; YAML-NEXT: Function: test
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; YAML-NEXT: Args:
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; YAML-NEXT: - String: 'Stores SLP vectorized with cost '
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; YAML-NEXT: - Cost: '-2'
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; YAML-NEXT: - String: ' and with tree size '
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; YAML-NEXT: - TreeSize: '2'
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define void @test(ptr %h) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[H:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[DCT2X211:%.*]] = alloca [0 x [0 x [8 x i64]]], i32 0, align 16
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; CHECK-NEXT: [[CHROMA_DC209:%.*]] = getelementptr i8, ptr [[H]], i64 0
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[DCT2X211]], align 16
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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; CHECK-NEXT: store <4 x i64> [[TMP1]], ptr [[CHROMA_DC209]], align 2
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; CHECK-NEXT: ret void
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;
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entry:
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%dct2x211 = alloca [0 x [0 x [8 x i64]]], i32 0, align 16
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%chroma_dc209 = getelementptr i8, ptr %h, i64 0
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%arrayidx30.i = getelementptr i8, ptr %dct2x211, i64 16
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%arrayidx33.i = getelementptr i8, ptr %dct2x211, i64 8
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%arrayidx36.i181 = getelementptr i8, ptr %dct2x211, i64 24
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%0 = load i64, ptr %dct2x211, align 16
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store i64 %0, ptr %chroma_dc209, align 2
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%1 = load i64, ptr %arrayidx30.i, align 4
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%arrayidx3.i224 = getelementptr i8, ptr %h, i64 8
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store i64 %1, ptr %arrayidx3.i224, align 2
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%2 = load i64, ptr %arrayidx33.i, align 2
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%arrayidx5.i226 = getelementptr i8, ptr %h, i64 16
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store i64 %2, ptr %arrayidx5.i226, align 2
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%3 = load i64, ptr %arrayidx36.i181, align 2
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%arrayidx7.i228 = getelementptr i8, ptr %h, i64 24
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store i64 %3, ptr %arrayidx7.i228, align 2
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ret void
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}
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