e914421d7f
If the scalars is used externally is in the root node, it may have incorrect signedness info because of the conflict with the demanded bits analysis. Need to perform exact signedness analysis and compute it rather than rely on the precomputed value, which might be incorrect for alternate zext/sext nodes. Fixes #113520
35 lines
1.8 KiB
LLVM
35 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -mtriple=systemz-unknown -mcpu=z15 < %s -slp-threshold=-10 | FileCheck %s
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define i32 @test(ptr %0, ptr %1) {
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; CHECK-LABEL: define i32 @test(
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; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr inttoptr (i64 32 to ptr), align 32
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; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP1]], align 8
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[TMP4]], i64 32
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; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8
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; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i32 0
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; CHECK-NEXT: [[TMP14:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP3]], i32 1
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ne <2 x i64> [[TMP14]], zeroinitializer
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; CHECK-NEXT: [[TMP16:%.*]] = sext <2 x i1> [[TMP9]] to <2 x i8>
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; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i1> [[TMP9]] to <2 x i8>
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; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i8> [[TMP16]], <2 x i8> [[TMP11]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i8> [[TMP12]], i32 0
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; CHECK-NEXT: [[DOTNEG:%.*]] = sext i8 [[TMP13]] to i32
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i8> [[TMP12]], i32 1
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; CHECK-NEXT: [[TMP8:%.*]] = zext i8 [[TMP15]] to i32
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; CHECK-NEXT: [[TMP10:%.*]] = add nsw i32 [[DOTNEG]], [[TMP8]]
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; CHECK-NEXT: ret i32 [[TMP10]]
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;
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%3 = load i64, ptr inttoptr (i64 32 to ptr), align 32
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%4 = load ptr, ptr %1, align 8
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%5 = getelementptr inbounds i8, ptr %4, i64 32
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%6 = load i64, ptr %5, align 8
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%7 = icmp ne i64 %3, 0
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%8 = zext i1 %7 to i32
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%9 = icmp ne i64 %6, 0
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%.neg = sext i1 %9 to i32
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%10 = add nsw i32 %.neg, %8
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ret i32 %10
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}
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