To run integration tests using qemu-aarch64 on x64 host, below flags are
added to the cmake command when building mlir/llvm:
-DMLIR_INCLUDE_INTEGRATION_TESTS=ON \
-DMLIR_RUN_ARM_SVE_TESTS=ON \
-DMLIR_RUN_ARM_SME_TESTS=ON \
-DARM_EMULATOR_EXECUTABLE="<...>/qemu-aarch64" \
-DARM_EMULATOR_OPTIONS="-L /usr/aarch64-linux-gnu" \
-DARM_EMULATOR_MLIR_CPU_RUNNER_EXECUTABLE="<llvm_arm64_build_top>/bin/mlir-cpu-runner-arm64"
\
-DARM_EMULATOR_LLI_EXECUTABLE="<llvm_arm64_build_top>/bin/lli" \
-DARM_EMULATOR_UTILS_LIB_DIR="<llvm_arm64_build_top>/lib"
The last three above are prebuilt on, or cross-built for, an aarch64
host.
This patch introduced substittutions of "%native_mlir_runner_utils" etc. and use
them in SVE/SME integration tests. When configured to run using qemu-aarch64,
mlir runtime util libs will be loaded from ARM_EMULATOR_UTILS_LIB_DIR, if set.
Some tests marked with 'UNSUPPORTED: target=aarch64{{.*}}' are still run
when configured with ARM_EMULATOR_EXECUTABLE and the default target is
not aarch64.
A lit config feature 'mlir_arm_emulator' is added in
mlir/test/lit.site.cfg.py.in and to UNSUPPORTED list of such tests.
151 lines
5.4 KiB
MLIR
151 lines
5.4 KiB
MLIR
//--------------------------------------------------------------------------------------------------
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// WHEN CREATING A NEW TEST, PLEASE JUST COPY & PASTE WITHOUT EDITS.
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//
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// Set-up that's shared across all tests in this directory. In principle, this
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// config could be moved to lit.local.cfg. However, there are downstream users that
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// do not use these LIT config files. Hence why this is kept inline.
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//
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// DEFINE: %{sparsifier_opts} = enable-runtime-library=true
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// DEFINE: %{sparsifier_opts_sve} = enable-arm-sve=true %{sparsifier_opts}
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// DEFINE: %{compile} = mlir-opt %s --sparsifier="%{sparsifier_opts}"
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// DEFINE: %{compile_sve} = mlir-opt %s --sparsifier="%{sparsifier_opts_sve}"
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// DEFINE: %{run_libs} = -shared-libs=%mlir_c_runner_utils,%mlir_runner_utils
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// DEFINE: %{run_libs_sve} = -shared-libs=%native_mlir_runner_utils,%native_mlir_c_runner_utils
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// DEFINE: %{run_opts} = -e main -entry-point-result=void
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// DEFINE: %{run} = mlir-cpu-runner %{run_opts} %{run_libs}
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// DEFINE: %{run_sve} = %mcr_aarch64_cmd --march=aarch64 --mattr="+sve" %{run_opts} %{run_libs_sve}
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//
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// DEFINE: %{env} =
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//--------------------------------------------------------------------------------------------------
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// RUN: %{compile} | %{run} | FileCheck %s
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//
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// Do the same run, but now with direct IR generation.
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// REDEFINE: %{sparsifier_opts} = enable-runtime-library=false enable-buffer-initialization=true
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// RUN: %{compile} | %{run} | FileCheck %s
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//
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// Do the same run, but now with vectorization.
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// REDEFINE: %{sparsifier_opts} = enable-runtime-library=false enable-buffer-initialization=true vl=2 reassociate-fp-reductions=true enable-index-optimizations=true
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// RUN: %{compile} | %{run} | FileCheck %s
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//
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// Do the same run, but now with VLA vectorization.
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// RUN: %if mlir_arm_sve_tests %{ %{compile_sve} | %{run_sve} | FileCheck %s %}
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#DCSR = #sparse_tensor.encoding<{
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map = (d0, d1) -> (d0 : compressed, d1 : compressed)
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}>
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#DCSC = #sparse_tensor.encoding<{
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map = (d0, d1) -> (d1 : compressed, d0 : compressed)
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}>
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#transpose_trait = {
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indexing_maps = [
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affine_map<(i,j) -> (j,i)>, // A
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affine_map<(i,j) -> (i,j)> // X
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],
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iterator_types = ["parallel", "parallel"],
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doc = "X(i,j) = A(j,i)"
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}
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module {
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//
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// Transposing a sparse row-wise matrix into another sparse row-wise
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// matrix introduces a cycle in the iteration graph. This complication
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// can be avoided by manually inserting a conversion of the incoming
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// matrix into a sparse column-wise matrix first.
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//
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func.func @sparse_transpose(%arga: tensor<3x4xf64, #DCSR>)
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-> tensor<4x3xf64, #DCSR> {
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%t = sparse_tensor.convert %arga
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: tensor<3x4xf64, #DCSR> to tensor<3x4xf64, #DCSC>
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%i = tensor.empty() : tensor<4x3xf64, #DCSR>
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%0 = linalg.generic #transpose_trait
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ins(%t: tensor<3x4xf64, #DCSC>)
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outs(%i: tensor<4x3xf64, #DCSR>) {
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^bb(%a: f64, %x: f64):
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linalg.yield %a : f64
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} -> tensor<4x3xf64, #DCSR>
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bufferization.dealloc_tensor %t : tensor<3x4xf64, #DCSC>
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return %0 : tensor<4x3xf64, #DCSR>
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}
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//
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// However, even better, the sparsifier is able to insert such a
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// conversion automatically to resolve a cycle in the iteration graph!
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//
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func.func @sparse_transpose_auto(%arga: tensor<3x4xf64, #DCSR>)
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-> tensor<4x3xf64, #DCSR> {
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%i = tensor.empty() : tensor<4x3xf64, #DCSR>
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%0 = linalg.generic #transpose_trait
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ins(%arga: tensor<3x4xf64, #DCSR>)
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outs(%i: tensor<4x3xf64, #DCSR>) {
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^bb(%a: f64, %x: f64):
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linalg.yield %a : f64
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} -> tensor<4x3xf64, #DCSR>
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return %0 : tensor<4x3xf64, #DCSR>
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}
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//
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// Main driver.
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//
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func.func @main() {
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%c0 = arith.constant 0 : index
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%c1 = arith.constant 1 : index
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%c4 = arith.constant 4 : index
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%du = arith.constant 0.0 : f64
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// Setup input sparse matrix from compressed constant.
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%d = arith.constant dense <[
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[ 1.1, 1.2, 0.0, 1.4 ],
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[ 0.0, 0.0, 0.0, 0.0 ],
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[ 3.1, 0.0, 3.3, 3.4 ]
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]> : tensor<3x4xf64>
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%a = sparse_tensor.convert %d : tensor<3x4xf64> to tensor<3x4xf64, #DCSR>
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// Call the kernels.
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%0 = call @sparse_transpose(%a)
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: (tensor<3x4xf64, #DCSR>) -> tensor<4x3xf64, #DCSR>
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%1 = call @sparse_transpose_auto(%a)
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: (tensor<3x4xf64, #DCSR>) -> tensor<4x3xf64, #DCSR>
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//
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// Verify result.
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//
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// CHECK: ---- Sparse Tensor ----
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// CHECK-NEXT: nse = 6
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// CHECK-NEXT: dim = ( 4, 3 )
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// CHECK-NEXT: lvl = ( 4, 3 )
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// CHECK-NEXT: pos[0] : ( 0, 4 )
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// CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 )
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// CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 6 )
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// CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 )
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// CHECK-NEXT: values : ( 1.1, 3.1, 1.2, 3.3, 1.4, 3.4 )
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// CHECK-NEXT: ----
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// CHECK: ---- Sparse Tensor ----
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// CHECK-NEXT: nse = 6
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// CHECK-NEXT: dim = ( 4, 3 )
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// CHECK-NEXT: lvl = ( 4, 3 )
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// CHECK-NEXT: pos[0] : ( 0, 4 )
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// CHECK-NEXT: crd[0] : ( 0, 1, 2, 3 )
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// CHECK-NEXT: pos[1] : ( 0, 2, 3, 4, 6 )
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// CHECK-NEXT: crd[1] : ( 0, 2, 0, 2, 0, 2 )
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// CHECK-NEXT: values : ( 1.1, 3.1, 1.2, 3.3, 1.4, 3.4 )
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// CHECK-NEXT: ----
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//
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sparse_tensor.print %0 : tensor<4x3xf64, #DCSR>
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sparse_tensor.print %1 : tensor<4x3xf64, #DCSR>
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// Release resources.
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bufferization.dealloc_tensor %a : tensor<3x4xf64, #DCSR>
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bufferization.dealloc_tensor %0 : tensor<4x3xf64, #DCSR>
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bufferization.dealloc_tensor %1 : tensor<4x3xf64, #DCSR>
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return
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}
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}
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