Matt Arsenault a41351e37c AMDGPU: Move hazard avoidance out of waitcnt pass. ...

This is mostly moving VMEM clause breaking into
the hazard recognizer. Also move another hazard
currently handled in the waitcnt pass.

Also stops breaking clauses unless xnack is enabled.

llvm-svn: 318557

2017-11-17 21:35:32 +00:00

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AArch64

[GISel]: DCE copy instructions during legalization

2017-11-17 02:44:55 +00:00

AMDGPU

AMDGPU: Move hazard avoidance out of waitcnt pass.

2017-11-17 21:35:32 +00:00

ARC

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ARM

[ARM] Use dwarf exception handling on MinGW

2017-11-17 08:04:40 +00:00

AVR

[AVR] Remove the select-mbb-placement-bug.ll test

2017-11-14 04:32:49 +00:00

BPF

bpf: print backward branch target properly

2017-11-16 19:15:36 +00:00

Generic

[CodeGen] Peel off the dominant case in switch statement in lowering

2017-11-14 21:44:09 +00:00

Hexagon

[Hexagon] Prefer L2_loadrub_io over L4_loadrub_rr

2017-11-02 21:56:59 +00:00

Inputs

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Lanai

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Mips

[mips] Improve genConstMult() to work with arbitrary precision

2017-11-15 15:24:04 +00:00

MIR

[MIRPrinter] Use %subreg.xxx syntax for subregister index operands

2017-11-06 21:46:06 +00:00

MSP430

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Nios2

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NVPTX

[NVPTX] Implement __nvvm_atom_add_gen_d builtin.

2017-11-07 22:10:54 +00:00

PowerPC

[PPC] Change i32 constant in store instruction to i64

2017-11-16 18:27:34 +00:00

RISCV

[RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py

2017-11-09 15:45:42 +00:00

SPARC

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SystemZ

[CodeGen] Peel off the dominant case in switch statement in lowering

2017-11-14 21:44:09 +00:00

Thumb

[ARM] Fix incorrect conversion of a tail call to an ordinary call

2017-11-14 10:36:52 +00:00

Thumb2

[arm] Fix Unnecessary reloads from GOT.

2017-11-13 20:45:38 +00:00

WebAssembly

[WebAssembly] Update cfg-stackify.ll to remove the workaround added in r318288.

2017-11-15 21:38:33 +00:00

WinEH

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X86

[X86] Merge scheduling tests for SHLD/SHRD

2017-11-17 18:35:49 +00:00

XCore

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