95e8ffd398
Summary: Allow the selection of BUFFER_LOAD_FORMAT_x and _XY. Do this now before the frontend patches land in Mesa. Eventually, we may want to automatically reduce the size of loads at the LLVM IR level, which requires such overloads, and in some cases Mesa can generate them directly. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18255 llvm-svn: 263792
131 lines
5.5 KiB
LLVM
131 lines
5.5 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}buffer_load:
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;CHECK: buffer_load_format_xyzw v[0:3], s[0:3], 0
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;CHECK: buffer_load_format_xyzw v[4:7], s[0:3], 0 glc
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;CHECK: buffer_load_format_xyzw v[8:11], s[0:3], 0 slc
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;CHECK: s_waitcnt
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define {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs:
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;CHECK: buffer_load_format_xyzw v[0:3], s[0:3], 0 offset:42
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_immoffs(<4 x i32> inreg) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
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;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 61 offset:4095
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;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7fff
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;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS1]] offset:4093
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;CHECK: s_mov_b32 [[OFS2:s[0-9]+]], 0x8fff
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;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS2]] offset:1
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) #0 {
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main_body:
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%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4156, i1 0, i1 0)
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%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36860, i1 0, i1 0)
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%d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0)
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%d.3 = fadd <4 x float> %d.0, %d.1
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%data = fadd <4 x float> %d.2, %d.3
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs_reuse:
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;CHECK: s_movk_i32 [[OFS:s[0-9]+]], 0xfff
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;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS]] offset:65
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;CHECK-NOT: s_mov
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;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS]] offset:81
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_immoffs_reuse(<4 x i32> inreg) #0 {
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main_body:
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%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0)
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%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0)
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%data = fadd <4 x float> %d.0, %d.1
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_idx:
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;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs:
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;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
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;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:58
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) #0 {
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main_body:
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%ofs = add i32 %1, 58
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_both:
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;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_both_reversed:
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;CHECK: v_mov_b32_e32 v2, v0
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;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) #0 {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x:
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;CHECK: buffer_load_format_x v0, s[0:3], 0
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;CHECK: s_waitcnt
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define float @buffer_load_x(<4 x i32> inreg %rsrc) #0 {
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main_body:
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%data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
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ret float %data
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}
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;CHECK-LABEL: {{^}}buffer_load_xy:
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;CHECK: buffer_load_format_xy v[0:1], s[0:3], 0
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;CHECK: s_waitcnt
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define <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) #0 {
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main_body:
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%data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
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ret <2 x float> %data
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}
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declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
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declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1
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declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readonly }
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