95e8ffd398
Summary: Allow the selection of BUFFER_LOAD_FORMAT_x and _XY. Do this now before the frontend patches land in Mesa. Eventually, we may want to automatically reduce the size of loads at the LLVM IR level, which requires such overloads, and in some cases Mesa can generate them directly. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18255 llvm-svn: 263792
79 lines
3.4 KiB
LLVM
79 lines
3.4 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}buffer_store:
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;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0
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;CHECK: buffer_store_format_xyzw v[4:7], s[0:3], 0 glc
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;CHECK: buffer_store_format_xyzw v[8:11], s[0:3], 0 slc
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define void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_immoffs:
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;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0 offset:42
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define void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_idx:
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;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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define void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_ofs:
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;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen
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define void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_both:
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;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
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define void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_both_reversed:
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;CHECK: v_mov_b32_e32 v6, v4
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;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
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define void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0)
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ret void
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}
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; Ideally, the register allocator would avoid the wait here
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;
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;CHECK-LABEL: {{^}}buffer_store_wait:
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;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0) expcnt(0)
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;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
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define void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
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%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
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call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1
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declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readonly }
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