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clang-p2996/llvm/test/CodeGen/Hexagon
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Simon Pilgrim a015635629 [Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns 
This should handle the basic integer min/max handling - the HVX ops are still TODO.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

Differential Revision: https://reviews.llvm.org/D92112
2020-11-25 19:02:17 +00:00
..
autohvx
[Hexagon] Handle additional shuffles that can be made perfect
2020-10-29 19:09:00 -05:00
intrinsics
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
loop-idiom
[Hexagon][NewPM] Port -hexagon-loop-idiom and add to pipeline
2020-11-20 09:34:37 -08:00
pipeliner
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vect
[Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR
2020-10-10 19:49:47 -05:00
64bit_tstbit.ll
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abi-padding-2.ll
[Hexagon] Reducing minimum alignment requirement
2020-06-24 10:28:37 -05:00
abi-padding.ll
[Hexagon] Reducing minimum alignment requirement
2020-06-24 10:28:37 -05:00
abs.ll
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absaddr-store.ll
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absimm.ll
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add_int_double.ll
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add_mpi_RRR.ll
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add-use.ll
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addaddi.ll
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addasl-address.ll
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addh-sext-trunc.ll
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addh-shifted.ll
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addh.ll
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addr-calc-opt.ll
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addr-mode-opt.ll
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addrmode-align.ll
Update LSR's logic that identifies a post-increment SCEV value.
2020-03-02 16:34:18 -06:00
addrmode-globoff.mir
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addrmode-immop.mir
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addrmode-indoff.ll
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addrmode-keepdeadphis.ll
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addrmode-keepdeadphis.mir
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addrmode-offset.ll
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addrmode-rr-to-io.mir
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addrmode.ll
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addsubcarry.ll
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adjust-latency-stackST.ll
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aggr-antidep-tied.ll
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aggr-copy-order.ll
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aggr-licm.ll
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aggressive_licm.ll
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align_Os.ll
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align_test.ll
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alu64.ll
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always-ext.ll
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anti-dep-partial.mir
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args.ll
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ashift-left-right.ll
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asr-rnd64.ll
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asr-rnd.ll
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assert-postinc-ptr-not-value.ll
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atomic-rmw-add.ll
Handle part-word LL/SC in atomic expansion pass
2020-04-28 10:07:39 -05:00
atomic-store-byte.ll
Align store conditional address
2020-07-30 10:42:00 -05:00
Atomics.ll
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avoid-predspill-calleesaved.ll
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avoid-predspill.ll
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avoidVectorLowering.ll
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bank-conflict-load.mir
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bank-conflict.mir
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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base-offset-stv4.ll
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bit-addr-align.mir
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bit-bitsplit-at.ll
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bit-bitsplit-regclass.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
bit-bitsplit-src.ll
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bit-bitsplit.ll
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bit-cmp0.mir
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bit-eval.ll
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bit-ext-sat.ll
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bit-extract-off.ll
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bit-extract.ll
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bit-extractu-half.ll
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bit-gen-rseq.ll
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bit-has.ll
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bit-loop-rc-mismatch.ll
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bit-loop.ll
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bit-phi.ll
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bit-rie.ll
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bit-skip-byval.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
bit-validate-reg.ll
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bit-visit-flowq.ll
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bitconvert-vector.ll
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bitmanip.ll
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bkfir.ll
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block-addr.ll
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block-address.ll
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block-ranges-nodef.ll
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blockaddr-fpic.ll
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branch-folder-hoist-kills.mir
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branch-non-mbb.ll
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branchfolder-insert-impdef.mir
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branchfolder-keep-impdef.ll
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BranchPredict.ll
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brcond-setne.ll
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brev_ld.ll
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brev_st.ll
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bss-local.ll
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bug6757-endloop.ll
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bug9049.ll
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bug9963.ll
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bug14859-iv-cleanup-lpad.ll
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bug14859-split-const-block-addr.ll
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bug15515-shuffle.ll
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bug17276.ll
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bug17386.ll
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bug18008.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
bug18491-optsize.ll
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bug19076.ll
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bug19119.ll
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bug19254-ifconv-vec.ll
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bug27085.ll
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bug31839.ll
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bug-aa4463-ifconv-vecpred.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
bug-allocframe-size.ll
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bug-hcp-tied-kill.ll
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bugAsmHWloop.ll
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build-vector-shuffle.ll
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build-vector-v4i8-zext.ll
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builtin-expect.ll
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builtin-prefetch-offset.ll
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builtin-prefetch.ll
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call-long1.ll
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call-ret-i1.ll
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call-v4.ll
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calling-conv-2.ll
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
calling-conv.ll
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
callR_noreturn.ll
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callr-dep-edge.ll
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cext-check.ll
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cext-ice.ll
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cext-opt-basic.mir
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cext-opt-negative-fi.mir
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
cext-opt-numops.mir
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cext-opt-range-assert.mir
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cext-opt-range-offset.mir
Simplify MachineVerifier's block-successor verification.
2020-06-06 22:30:51 -04:00
cext-opt-shifted-range.mir
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cext-opt-stack-no-rr.mir
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cext-unnamed-global.mir
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cext-valid-packet1.ll
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cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfgopt-fall-through.ll
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cfi_offset2.ll
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cfi_offset.ll
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cfi-late-and-regpressure-init.ll
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cfi-late.ll
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cfi-offset.ll
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check-dot-new.ll
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check-subregister-for-latency.ll
Handle cases for subregisters.
2020-04-30 20:32:33 -05:00
checktabs.ll
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circ_ld.ll
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circ_ldd_bug.ll
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circ_ldw.ll
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circ_new.ll
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circ_pcr_assert.ll
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circ_st.ll
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circ-load-isel.ll
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clr_set_toggle.ll
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cmp_pred2.ll
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cmp_pred_reg.ll
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cmp_pred.ll
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cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll
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cmpb_gtu.ll
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cmpb_pred.ll
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cmpb-dec-imm.ll
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cmpb-eq.ll
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cmpbeq.ll
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cmph-gtu.ll
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cmpy-round.ll
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coalesce_tfri.ll
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coalescing-hvx-across-calls.ll
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combine_ir.ll
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combine_lh.ll
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combine-imm-ext2.ll
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combine-imm-ext.ll
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combine.ll
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combiner-lts.ll
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common-gep-basic.ll
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common-gep-icm.ll
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common-gep-inbounds.ll
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common-global-addr.ll
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compound.ll
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concat-vectors-legalize.ll
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const64.ll
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const-combine.ll
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const-pool-tf.ll
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constant_compound.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
constext-call.ll
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constext-immstore.ll
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constext-replace.ll
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constp-andir-global.mir
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constp-clb.ll
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constp-combine-neg.ll
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constp-ctb.ll
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constp-extract.ll
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constp-physreg.ll
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constp-rewrite-branches.ll
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constp-rseq.ll
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constp-vsplat.ll
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convert_const_i1_to_i8.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
convert-to-dot-old.ll
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convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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copy-to-combine-dbg.ll
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count_0s.ll
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countbits-basic.ll
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csr_stub_calls_dwarf_frame_info.ll
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csr-func-usedef.ll
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csr-stubs-spill-threshold.ll
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ctor.ll
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dadd.ll
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dag-combine-select-or0.ll
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dag-indexed.ll
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dccleana.ll
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dead-store-stack.ll
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dealloc_return.ll
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dealloc-store.ll
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debug-line_table_start.ll
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debug-prologue-loc.ll
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debug-prologue.ll
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def-undef-deps.ll
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default-align.ll
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deflate.ll
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df-min-max.ll
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
dfp.ll
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dhry_proc8.ll
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dhry_stall.ll
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dhry.ll
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disable-const64-tinycore.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
disable-const64.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
dmul.ll
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dont_rotate_pregs_at_O2.ll
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double.ll
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dsub.ll
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dualstore.ll
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duplex-addi-global-imm.mir
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duplex.ll
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dwarf-discriminator.ll
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early-if-conv-lifetime.mir
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early-if-conversion-bug1.ll
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early-if-debug.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
early-if-low8.mir
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early-if-merge-loop.ll
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early-if-phi-i1.ll
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early-if-predicator.mir
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early-if-spare.ll
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early-if-vecpi.ll
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early-if-vecpred.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
early-if.ll
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eh_return-r30.ll
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eh_return.ll
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eh_save_restore.ll
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ehabi.ll
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eliminate-pred-spill.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
entryBB-isLoopHdr.ll
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expand-condsets-basic.ll
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expand-condsets-copy-lis.ll
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expand-condsets-dead-bad.ll
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expand-condsets-dead-pred.ll
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expand-condsets-dead.ll
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expand-condsets-def-undef.mir
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expand-condsets-extend.ll
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expand-condsets-imm.mir
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expand-condsets-impuse2.mir
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expand-condsets-impuse.mir
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expand-condsets-phys-reg.mir
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expand-condsets-pred-undef2.ll
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expand-condsets-pred-undef.ll
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
expand-condsets-rm-reg.mir
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expand-condsets-rm-segment.ll
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expand-condsets-same-inputs.mir
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expand-condsets-undef2.ll
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expand-condsets-undef.ll
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expand-condsets-undefvni.ll
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expand-condsets.ll
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expand-copyw-undef.mir
[Hexagon] Recognize undefined registers in expandPostRAPseudo
2020-03-06 08:27:42 -06:00
expand-vselect-kill.mir
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expand-vstorerw-undef2.ll
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expand-vstorerw-undef.ll
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expand-wselect.mir
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extload-combine.ll
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extlow.ll
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extract_0bits.ll
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extract-basic.ll
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extractu_0bits.ll
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fadd.ll
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fcmp.ll
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feature-compound.ll
[Hexagon] Add a target feature to disable compound instructions
2020-01-16 12:37:30 -06:00
feature-memops.ll
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find-loop-instr.ll
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find-loop.ll
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fixed-spill-mutable.ll
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float-amode.ll
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float-bitcast.ll
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float-const64-G0.ll
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float-gen-cmpop.ll
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float.ll
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floatconvert-ieee-rnd-near.ll
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fltnvjump.ll
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fmadd.ll
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fminmax-v67.ll
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
fminmax.ll
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fmul-v67.ll
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
fmul.ll
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formal-args-i1.ll
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fp_latency.ll
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fpelim-basic.ll
Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351
2019-12-24 16:27:51 -08:00
frame-offset-overflow.ll
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fsel.ll
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fsub.ll
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funnel-shift2.ll
[Hexagon] Correct the order of operands when lowering funnel shift-left
2020-07-28 21:22:41 -05:00
funnel-shift.ll
[Hexagon] Correct the order of operands when lowering funnel shift-left
2020-07-28 21:22:41 -05:00
fusedandshift.ll
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generic-cpu.ll
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getBlockAddress.ll
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glob-align-volatile.ll
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global64bitbug.ll
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global-const-gep.ll
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global-ctor-pcrel.ll
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gp-plus-offset-load.ll
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gp-plus-offset-store.ll
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gp-rel.ll
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Halide_vec_cast_trunc1.ll
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Halide_vec_cast_trunc2.ll
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hasfp-crash1.ll
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hasfp-crash2.ll
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hello-world-v55.ll
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hello-world-v60.ll
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hexagon_cfi_offset.ll
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hexagon_vector_loop_carried_reuse_commutative.ll
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hexagon_vector_loop_carried_reuse_constant.ll
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hexagon_vector_loop_carried_reuse_invalid.ll
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hexagon_vector_loop_carried_reuse.ll
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hexagon-cond-jumpr31.ll
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hexagon-tfr-add.ll
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hexagon-verify-implicit-use.ll
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hidden-relocation.ll
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honor-optsize.ll
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hrc-stack-coloring.ll
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hvx-bitcast-v64i1.ll
[Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX
2020-08-26 13:10:22 -05:00
hvx-byte-store-double.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
hvx-byte-store.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
hvx-dbl-dual-output.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
hvx-double-vzero.ll
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hvx-dual-output.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
hvx-isel-vselect-v256i16.ll
[Hexagon] Check if EVT is simple type in HVX lowering
2020-08-25 15:02:44 -05:00
hvx-loopidiom-memcpy.ll
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hvx-nontemporal.ll
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hvx-vzero.ll
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hwloop1.ll
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hwloop2.ll
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hwloop3.ll
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hwloop4.ll
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hwloop5.ll
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hwloop-cleanup.ll
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hwloop-const.ll
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hwloop-crit-edge.ll
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hwloop-dbg.ll
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hwloop-ice.ll
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hwloop-le.ll
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hwloop-long.ll
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hwloop-loop1.ll
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hwloop-lt1.ll
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hwloop-lt.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-noreturn-call.ll
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hwloop-ph-deadcode.ll
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hwloop-phi-subreg.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll
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hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-redef-imm.mir
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hwloop-subreg.ll
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hwloop-swap.ll
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hwloop-with-return-call.ll
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hwloop-wrap2.ll
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hwloop-wrap.ll
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hx_V6_lo_hi.ll
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i1_VarArg.ll
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i8_VarArg.ll
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i16_VarArg.ll
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i128-bitop.ll
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idxload-with-zero-offset.ll
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ifcvt-common-kill.mir
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ifcvt-diamond-bad.ll
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ifcvt-diamond-bug-2016-08-26.ll
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ifcvt-diamond-ret.mir
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ifcvt-edge-weight.ll
[llc] (almost) remove --print-machineinstrs
2020-07-20 10:43:28 -07:00
ifcvt-impuse-livein.mir
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ifcvt-live-subreg.mir
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ifcvt-simple-bprob.ll
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ignore-terminal-mbb.ll
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indirect-br.ll
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initial-exec.ll
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inline-asm-a.ll
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inline-asm-bad-constraint.ll
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inline-asm-clobber-lr.ll
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inline-asm-error.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
inline-asm-filetype-null.ll
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inline-asm-hexagon.ll
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inline-asm-i1.ll
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inline-asm-qv.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
inline-asm-vecpred128.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
inlineasm-output-template.ll
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insert4.ll
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insert-basic.ll
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insert.ll
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intrinsics-v60-alu.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
intrinsics-v60-misc.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
intrinsics-v60-permute.ll
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intrinsics-v60-shift.ll
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intrinsics-v60-vcmp.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
intrinsics-v60-vmpy-acc-128B.ll
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intrinsics-v60-vmpy-acc.ll
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intrinsics-v60-vmpy.ll
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intrinsics-v66.ll
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intrinsics-v67.ll
[Hexagon] Add support for Hexagon/HVX v67 ISA
2020-01-20 16:16:49 -06:00
invalid-dotnew-attempt.mir
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invalid-memrefs.ll
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is-legal-void.ll
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isel-bitcast-v8i1-i8.ll
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isel-bitcast-v8i8-v4i16.ll
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isel-combine-half.ll
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isel-dcfetch-intrin-map.ll
[Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch
2020-02-28 14:19:20 -06:00
isel-exti1.ll
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isel-global-offset-alignment.ll
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isel-hvx-pred-bitcast-order.ll
[Hexagon] Fix perfect shuffle generation for single vectors
2020-08-30 06:43:16 -05:00
isel-i1arg-crash.ll
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isel-minmax-v64bit.ll
[Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns
2020-11-25 19:02:17 +00:00
isel-op-zext-i1.ll
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isel-prefer.ll
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isel-select-v4i8.ll
[Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing
2020-02-11 15:27:33 -06:00
isel-setcc-i1.ll
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isel-simplify-crash.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
isel-splat-vector-crash.ll
[Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR
2020-10-10 19:49:47 -05:00
isel-splat-vector-dag-crash.ll
[Hexagon] Replace HexagonISD::VSPLAT with ISD::SPLAT_VECTOR
2020-10-10 19:49:47 -05:00
isel-uaddo-1.ll
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isel-vacopy.ll
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isel-vlsr-v2i16.ll
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isel-vselect-v4i8.ll
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isel-zext-vNi1.ll
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jt-in-text.ll
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jump-prob.ll
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jump-table-g0.ll
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jump-table-isel.ll
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large-number-of-preds.ll
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late_instr.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
late-pred.ll
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lcomm.ll
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lit.local.cfg
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livephysregs-add-pristines.mir
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livephysregs-lane-masks2.mir
[Hexagon] Add missing live-in registers in some codegen tests
2020-04-23 10:28:04 -05:00
livephysregs-lane-masks.mir
[Hexagon] Add missing live-in registers in some codegen tests
2020-04-23 10:28:04 -05:00
livephysregs-regmask-clobber.mir
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load-abs.ll
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loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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local-exec.ll
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long-calls.ll
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loop_correctness.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
loop-prefetch.ll
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loop-rotate-bug.ll
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loop-rotate-liveins.ll
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lower-extract-subvector.ll
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lower-i1.ll
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lsr-post-inc-cross-use-offsets.ll
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lsr-postinc-nested-loop.ll
Update LSR's logic that identifies a post-increment SCEV value.
2020-03-02 16:34:18 -06:00
M4_mpyri_addi_global.ll
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M4_mpyrr_addi_global.ll
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machine-cp-clobbers.mir
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machine-sink.ll
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macint.ll
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maddsubu.ll
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mapped_intrinsics.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
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maxw.ll
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mem-fi-add.ll
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mem-load-circ.ll
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mem-ops-sub_01.ll
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mem-ops-sub_i16_01.ll
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mem-ops-sub_i16.ll
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mem-ops-sub.ll
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memcmp.ll
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memcpy-likely-aligned.ll
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memcpy-memmove-inline.ll
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memop-bit18.ll
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memops1.ll
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memops2.ll
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memops3.ll
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memops_global.ll
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memops-stack.ll
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memops.ll
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memset-inline.ll
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mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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mipi-double-small.ll
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misaligned_double_vector_store_not_fast.ll
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misaligned-access.ll
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misaligned-const-load.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
misaligned-const-store.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
misched-top-rptracker-sync.ll
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mlong-calls.ll
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mnaci_v66.ll
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mpy.ll
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mpysin-imm.ll
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mul64-sext.ll
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mul64.ll
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mulh.ll
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mulhs.ll
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multi-cycle.ll
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mux-basic.ll
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mux-kill1.mir
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mux-kill2.mir
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mux-kill3.mir
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mux-undef.ll
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muxii-bug.ll
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muxii-crash.ll
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namedreg.ll
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neg.ll
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newify-crash.ll
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newvaluejump2.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
newvaluejump3.ll
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newvaluejump-c4.mir
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newvaluejump-float.mir
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newvaluejump-kill2.mir
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newvaluejump-kill.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
newvaluejump-postinc.ll
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newvaluejump-solo.mir
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newvaluejump.ll
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newvalueSameReg.ll
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newvaluestore2.ll
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newvaluestore.ll
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no_struct_element.ll
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no-falign-function-for-size.ll
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no-packets-gather.ll
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no-packets.ll
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noFalignAfterCallAtO2.ll
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noreturn-noepilog.ll
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noreturn-notail.ll
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noreturn-stack-elim.ll
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not-op.ll
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ntstbit.ll
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nv_store_vec.ll
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NVJumpCmp.ll
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opt-addr-mode-subreg-use.ll
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
opt-addr-mode.ll
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opt-fabs.ll
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opt-fneg.ll
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opt-glob-addrs-000.ll
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opt-glob-addrs-001.ll
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opt-glob-addrs-003.ll
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opt-sext-intrinsics.ll
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opt-spill-volatile.ll
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optimize-mux.ll
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P08214.ll
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packed-store.ll
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packetize_cond_inst.ll
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packetize-allocframe.ll
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packetize-call-r29.ll
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packetize-cfi-location.ll
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packetize-dccleana.mir
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packetize-debug-loc.mir
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packetize-frame-setup-destroy.mir
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packetize-impdef-1.ll
[Hexagon] Use InstSimplify instead of ConstantProp
2020-08-04 15:42:39 -07:00
packetize-impdef.ll
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packetize-l2fetch.ll
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packetize-load-store-aliasing.mir
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packetize-nvj-no-prune.mir
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packetize-nvstore.mir
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packetize-return-arg.ll
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packetize-tailcall-arg.ll
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packetize-update-offset.mir
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packetize-vgather-slot01.mir
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packetize-volatiles.ll
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packetizer-resources.ll
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partword-cmpxchg.ll
Handle part-word LL/SC in atomic expansion pass
2020-04-28 10:07:39 -05:00
peephole-kill-flags.ll
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peephole-move-phi.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
peephole-op-swap.ll
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phi-elim.ll
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pic-jt-big.ll
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pic-jumptables.ll
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pic-local.ll
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pic-regusage.ll
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pic-sdata.ll
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pic-simple.ll
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pic-static.ll
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plt-rel.ll
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pmpyw_acc.ll
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post-inc-aa-metadata.ll
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post-ra-kill-update.mir
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postinc-aggr-dag-cycle.ll
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postinc-baseoffset.mir
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postinc-float.ll
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postinc-load.ll
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postinc-offset.ll
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postinc-order.ll
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postinc-store.ll
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postra-sink-subregs.mir
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PR33749.ll
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pred-absolute-store.ll
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pred-gp.ll
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pred-instrs.ll
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pred-sched.ll
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pred-simp.ll
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pred-taken-jump.ll
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predicate-copy.ll
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predicate-logical.ll
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predicate-rcmp.ll
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predtfrs.ll
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prefetch-intr.ll
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prefetch-shuffler-ice.ll
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prob-types.ll
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prof-early-if.ll
Revert "Include static prof data when collecting loop BBs"
2020-03-24 09:41:16 -07:00
propagate-vcombine.ll
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ps_call_nr.ll
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rdf-copy-renamable-reserved.mir
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rdf-copy-undef2.ll
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rdf-copy-undef.ll
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rdf-copy.ll
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rdf-cover-use.ll
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rdf-dead-loop.ll
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rdf-def-mask.ll
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rdf-ehlabel-live.mir
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rdf-extra-livein.ll
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rdf-filter-defs.ll
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rdf-ignore-undef.ll
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rdf-inline-asm-fixed.ll
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rdf-inline-asm.ll
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rdf-kill-last-op.ll
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rdf-multiple-phis-up.ll
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rdf-phi-shadows.ll
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rdf-phi-up.ll
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rdf-reset-kills.ll
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readcyclecounter.ll
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redundant-branching2.ll
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reg_seq.ll
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reg-by-name.ll
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reg-eq-cmp.ll
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reg-scav-imp-use-dbl-vec.ll
…
reg-scavengebug-2.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
reg-scavengebug-3.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
reg-scavengebug-4.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
reg-scavengebug-5.ll
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reg-scavengebug.ll
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reg-scavenger-valid-slot.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
regalloc-bad-undef.mir
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regalloc-block-overlap.ll
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regalloc-coal-extend-short-subrange.mir
[RegisterCoalescer] Extend a subrange if needed when filling range gap
2020-05-04 16:49:59 -05:00
regalloc-coal-fullreg-undef.mir
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regalloc-liveout-undef.mir
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registerpassbuildercallbacks.ll
[NPM] Add target specific hook to add passes for New Pass Manager
2020-09-30 13:29:43 -07:00
registerscav-missing-spill-slot.ll
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registerscavenger-fail1.ll
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regp-underflow.ll
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regscav-wrong-super-sub-regs.ll
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regscavenger_fail_hwloop.ll
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regscavengerbug.ll
OpaquePtr: Update more tests to use typed sret
2020-11-20 20:08:43 -05:00
relax.ll
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remove_lsr.ll
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remove-endloop.ll
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restore-single-reg.ll
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ret-struct-by-val.ll
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retval-redundant-copy.ll
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rotate-multi.ll
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rotate.ll
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rotl-i64.ll
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runtime-stkchk.ll
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S3_2op.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
save-kill-csr.ll
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save-regs-thresh.ll
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sdata-array.ll
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sdata-basic.ll
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sdata-expand-const.ll
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sdata-explicit-section.ll
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sdata-load-size.ll
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sdata-opaque-type.ll
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sdata-stack-guard.ll
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sdiv-minsigned.ll
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sdr-basic.ll
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sdr-global.mir
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sdr-nosplit1.ll
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sdr-reg-profit.ll
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sdr-shr32.ll
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section_7275.ll
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select-instr-align.ll
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setmemrefs.ll
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sf-min-max.ll
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sffms.ll
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sfmin_dce.ll
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sfmpyacc_scale.ll
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shrink-frame-basic.ll
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signed_immediates.ll
…
signext-inreg.ll
[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'
2020-01-03 03:26:41 +00:00
simple_addend.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
simpletailcall.ll
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simplify64bitops_7223.ll
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spill-vector-alignment.mir
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split-const32-const64.ll
…
split-muxii.ll
…
split-vecpred.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
stack-align1.ll
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stack-align2.ll
…
stack-align-reset.ll
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stack-alloca1.ll
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stack-alloca2.ll
…
stack-guard-acceptable-type.ll
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static.ll
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store1.ll
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store_abs.ll
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store-abs.ll
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store-AbsSet.ll
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store-constant.ll
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store-imm-amode.ll
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store-imm-byte.ll
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store-imm-halword.ll
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store-imm-large-stack.ll
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store-imm-stack-object.ll
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store-imm-word.ll
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store-shift.ll
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store-vector-pred.ll
[Hexagon] Implement llvm.masked.load and llvm.masked.store for HVX
2020-08-26 13:10:22 -05:00
store-widen-aliased-load.ll
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store-widen-negv2.ll
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store-widen-negv.ll
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store-widen-subreg.ll
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store-widen.ll
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storerd-io-over-rr.ll
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storerinewabs.ll
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struct_args_large.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
struct_args.ll
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struct_copy_sched_r16.ll
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struct_copy.ll
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struct-const.ll
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sub-add.ll
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subh-shifted.ll
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subh.ll
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subi-asl.ll
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SUnit-boundary-prob.ll
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switch-lut-explicit-section.ll
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switch-lut-function-section.ll
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switch-lut-multiple-functions.ll
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switch-lut-text-section.ll
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swp-art-deps-rec.ll
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swp-bad-sched.ll
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swp-badorder.ll
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swp-carried-1.ll
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swp-carried-dep1.mir
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swp-carried-dep2.mir
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swp-chain-refs.ll
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swp-change-dep1.ll
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swp-change-dep-cycle.ll
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swp-change-dep.ll
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swp-change-deps.ll
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swp-check-offset.ll
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swp-const-tc1.ll
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swp-const-tc2.ll
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swp-const-tc3.ll
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swp-const-tc.ll
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swp-conv3x3-nested.ll
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swp-copytophi-dag.ll
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swp-crash-iter.ll
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swp-cse-phi.ll
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swp-dag-phi1.ll
…
swp-dag-phi.ll
…
swp-dead-regseq.ll
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swp-dep-neg-offset.ll
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swp-disable-Os.ll
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swp-epilog-numphis.ll
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swp-epilog-phi2.ll
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swp-epilog-phi4.ll
…
swp-epilog-phi5.ll
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swp-epilog-phi6.ll
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swp-epilog-phi7.ll
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swp-epilog-phi8.ll
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swp-epilog-phi9.ll
…
swp-epilog-phi10.ll
…
swp-epilog-phi11.ll
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swp-epilog-phi12.ll
…
swp-epilog-phi13.ll
[ModuloSchedule] Fix epilogue peeling with illegal phi.
2020-05-07 10:04:05 -07:00
swp-epilog-reuse2.ll
…
swp-epilog-reuse3.ll
…
swp-epilog-reuse4.ll
…
swp-epilog-reuse-1.ll
…
swp-epilog-reuse.ll
…
swp-exit-fixup.ll
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swp-fix-last-use1.ll
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swp-fix-last-use.ll
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swp-intreglow8.ll
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swp-kernel-last-use.ll
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swp-kernel-phi1.ll
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swp-large-rec.ll
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swp-listen-loop3.ll
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swp-loop-carried-crash.ll
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swp-loop-carried-unknown.ll
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swp-loop-carried.ll
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swp-loopval.ll
…
swp-lots-deps.ll
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swp-matmul-bitext.ll
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swp-max-stage3.ll
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swp-max.ll
…
swp-maxstart.ll
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swp-memrefs-epilog.ll
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swp-more-phi.ll
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swp-multi-loops.ll
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swp-multi-phi-refs.ll
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swp-new-phi.ll
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swp-node-order.ll
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swp-order1.ll
…
swp-order-carried.ll
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swp-order-copies.ll
…
swp-order-deps1.ll
…
swp-order-deps3.ll
…
swp-order-deps4.ll
…
swp-order-deps5.ll
…
swp-order-deps6.ll
…
swp-order-deps7.ll
…
swp-order-prec.ll
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swp-order.ll
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swp-phi-ch-offset.ll
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swp-phi-chains.ll
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swp-phi-def-use.ll
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swp-phi-dep1.ll
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swp-phi-dep.ll
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swp-phi-order.ll
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swp-phi-ref1.ll
…
swp-phi-ref.ll
…
swp-phi-start.ll
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swp-phi.ll
…
swp-physreg.ll
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swp-pragma-disable-bug.ll
[Pipeliner] Fix the bug in pragma that disables the pipeliner.
2020-04-10 12:52:16 -05:00
swp-pragma-disable.ii
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swp-pragma-initiation-interval-reset.ii
[MachinePipeliner] Fix II_setByPragma initialization
2020-09-09 13:38:35 +00:00
swp-pragma-initiation-interval.ii
…
swp-prolog-phi4.ll
…
swp-prolog-phi.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
swp-regseq.ll
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swp-remove-dep-ice.ll
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swp-rename-dead-phi.ll
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swp-rename.ll
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swp-replace-uses1.ll
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swp-resmii-1.ll
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swp-resmii.ll
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swp-reuse-phi-1.ll
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swp-reuse-phi-2.ll
…
swp-reuse-phi-4.ll
…
swp-reuse-phi-5.ll
…
swp-reuse-phi-6.ll
…
swp-reuse-phi.ll
…
swp-sigma.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
swp-stages3.ll
…
swp-stages4.ll
…
swp-stages5.ll
…
swp-stages.ll
…
swp-subreg.ll
…
swp-swap.ll
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swp-tfri.ll
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swp-vect-dotprod.ll
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swp-vmult.ll
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swp-vsum.ll
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swp-xxh2.ll
…
tail-call-mem-intrinsics.ll
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tail-call-trunc.ll
…
tail-dup-subreg-abort.ll
…
tail-dup-subreg-map.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
tailcall_fastcc_ccc.ll
…
target-flag-ext.mir
…
tc_duplex_asm.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
tc_duplex.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
tc_sched1.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
tc_sched.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
tcm-zext.ll
…
testbits.ll
…
tfr-cleanup.ll
…
tfr-mux-nvj.ll
…
tfr-to-combine.ll
…
tied_oper.ll
…
tiny_bkfir_artdeps.ll
[Hexagon] Add REQUIRES: asserts to a testcase using -debug-only
2020-01-21 13:22:01 -06:00
tiny_bkfir_loop_align.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
tinycore.ll
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
2020-01-21 11:35:10 -06:00
tls_gd.ll
…
tls_pic.ll
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tls_static.ll
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trap-crash.ll
…
trap-unreachable.ll
…
trivialmemaliascheck.ll
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trunc-mpy.ll
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tstbit.ll
…
two-addr-tied-subregs.mir
…
two-crash.ll
…
twoaddressbug.ll
…
undef-ret.ll
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undo-dag-shift.ll
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union-1.ll
…
unordered-fcmp.ll
…
unreachable-mbb-phi-subreg.mir
…
upper-mpy.ll
…
usr-ovf-dep.ll
…
v5_insns.ll
…
v6-inlasm1.ll
…
v6-inlasm2.ll
…
v6-inlasm3.ll
…
v6-inlasm4.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6-shuffl.ll
…
v6-spill1.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6-unaligned-spill.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6-vecpred-copy.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6vassignp.ll
…
v6vec_inc1.ll
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v6vec_zero.ll
…
v6vec-vmemcur-prob.mir
…
v6vec-vmemu1.ll
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v6vec-vmemu2.ll
…
v6vec-vprint.ll
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v6vec-vshuff.ll
…
v6vect-dbl-fail1.ll
…
v6vect-dbl-spill.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6vect-dbl.ll
…
v6vect-dh1.ll
…
v6vect-locals1.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
v6vect-no-sideeffects.ll
…
v6vect-pred2.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6vect-spill-kill.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v6vect-vmem1.ll
…
v6vect-vsplat.ll
…
v60_Q6_P_rol_PI.ll
…
v60_sort16.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v60-align.ll
…
v60-cur.ll
…
v60-haar-postinc.ll
…
v60-halide-vcombinei8.ll
…
v60-vec-128b-1.ll
…
v60-vecpred-spill.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v60-vsel1.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v60-vsel2.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v60Intrins.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
v60rol-instrs.ll
…
v60small.ll
[Hexagon] Fix match pattern in a testcase
2020-03-09 09:09:58 -05:00
v60Vasr.ll
…
v62-CJAllSlots.ll
…
v62-inlasm4.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
V60-VDblNew.ll
…
vacopy.ll
Add support for Linux/Musl ABI
2020-01-20 09:59:56 -06:00
vadd1.ll
…
vaddh.ll
…
validate-offset.ll
…
vararg_align_check.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
vararg_double_onstack.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
vararg_named.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
vararg-deallocate-sp.ll
Add support for Linux/Musl ABI
2020-01-20 09:59:56 -06:00
vararg-formal.ll
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vararg-linux-abi.ll
Add support for Linux/Musl ABI
2020-01-20 09:59:56 -06:00
vararg.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
varargs-memv.ll
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vassign-to-combine.ll
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vcombine128_to_req_seq.ll
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vcombine_subreg.ll
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vcombine_to_req_seq.ll
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vdmpy-halide-test.ll
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vdotprod.ll
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vec-align.ll
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vec-call-full1.ll
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vec-pred-spill1.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
vec-vararg-align.ll
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vecPred2Vec.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
vect_setcc_v2i16.ll
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vect_setcc.ll
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vect-any_extend.ll
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vect-dbl-post-inc.ll
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vect-downscale.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
vect-regpairs.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
vect-set_cc_v2i32.ll
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vect-vd0.ll
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vect-zero_extend.ll
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vector-align.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
vector-ext-load.ll
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verify-liveness-at-def.mir
Extend LaneBitmask to 64 bit
2020-03-02 12:10:52 -08:00
verify-sink-code.ll
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verify-undef.ll
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vextract-basic.mir
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vgather-packetize.mir
[Hexagon] Add missing live-in registers in some codegen tests
2020-04-23 10:28:04 -05:00
vload-postinc-sel.ll
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vmemu-128.ll
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vmpa-halide-test.ll
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vpack_eo.ll
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vrcmpys.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
vselect-pseudo.ll
[Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1
2020-02-19 14:14:56 -06:00
vsplat-ext.ll
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vsplat-isel.ll
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wcsrtomb.ll
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zextloadi1.ll
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