1c466477ad
Currenlty assume x18 is used as pointer to shadow call stack. User shall pass flags: "-fsanitize=shadow-call-stack -ffixed-x18" Runtime supported is needed to setup x18. If SCS is desired, all parts of the program should be built with -ffixed-x18 to maintain inter-operatability. There's no particuluar reason that we must use x18 as SCS pointer. Any register may be used, as long as it does not have designated purpose already, like RA or passing call arguments. Differential Revision: https://reviews.llvm.org/D84414
175 lines
4.5 KiB
LLVM
175 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64
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define void @f1() shadowcallstack {
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; RV32-LABEL: f1:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f1:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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ret void
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}
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declare void @foo()
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define void @f2() shadowcallstack {
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; RV32-LABEL: f2:
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; RV32: # %bb.0:
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; RV32-NEXT: tail foo
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;
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; RV64-LABEL: f2:
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; RV64: # %bb.0:
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; RV64-NEXT: tail foo
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tail call void @foo()
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ret void
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}
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declare i32 @bar()
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define i32 @f3() shadowcallstack {
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; RV32-LABEL: f3:
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; RV32: # %bb.0:
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; RV32-NEXT: sw ra, 0(s2)
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; RV32-NEXT: addi s2, s2, 4
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: call bar
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(s2)
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; RV32-NEXT: addi s2, s2, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f3:
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; RV64: # %bb.0:
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; RV64-NEXT: sd ra, 0(s2)
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; RV64-NEXT: addi s2, s2, 8
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: sd ra, 8(sp)
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: call bar
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ld ra, -8(s2)
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; RV64-NEXT: addi s2, s2, -8
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; RV64-NEXT: ret
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%res = call i32 @bar()
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%res1 = add i32 %res, 1
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ret i32 %res
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}
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define i32 @f4() shadowcallstack {
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; RV32-LABEL: f4:
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; RV32: # %bb.0:
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; RV32-NEXT: sw ra, 0(s2)
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; RV32-NEXT: addi s2, s2, 4
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: sw s0, 8(sp)
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; RV32-NEXT: sw s1, 4(sp)
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; RV32-NEXT: sw s3, 0(sp)
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: .cfi_offset s1, -12
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; RV32-NEXT: .cfi_offset s3, -16
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; RV32-NEXT: call bar
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; RV32-NEXT: mv s3, a0
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; RV32-NEXT: call bar
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; RV32-NEXT: mv s1, a0
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; RV32-NEXT: call bar
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; RV32-NEXT: mv s0, a0
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; RV32-NEXT: call bar
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; RV32-NEXT: add a1, s3, s1
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; RV32-NEXT: add a0, s0, a0
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; RV32-NEXT: add a0, a1, a0
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; RV32-NEXT: lw s3, 0(sp)
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; RV32-NEXT: lw s1, 4(sp)
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; RV32-NEXT: lw s0, 8(sp)
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(s2)
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; RV32-NEXT: addi s2, s2, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f4:
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; RV64: # %bb.0:
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; RV64-NEXT: sd ra, 0(s2)
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; RV64-NEXT: addi s2, s2, 8
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; RV64-NEXT: addi sp, sp, -32
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; RV64-NEXT: .cfi_def_cfa_offset 32
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; RV64-NEXT: sd ra, 24(sp)
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; RV64-NEXT: sd s0, 16(sp)
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; RV64-NEXT: sd s1, 8(sp)
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; RV64-NEXT: sd s3, 0(sp)
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: .cfi_offset s1, -24
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; RV64-NEXT: .cfi_offset s3, -32
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; RV64-NEXT: call bar
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; RV64-NEXT: mv s3, a0
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; RV64-NEXT: call bar
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; RV64-NEXT: mv s1, a0
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; RV64-NEXT: call bar
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; RV64-NEXT: mv s0, a0
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; RV64-NEXT: call bar
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; RV64-NEXT: add a1, s3, s1
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; RV64-NEXT: add a0, s0, a0
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; RV64-NEXT: addw a0, a1, a0
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; RV64-NEXT: ld s3, 0(sp)
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; RV64-NEXT: ld s1, 8(sp)
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; RV64-NEXT: ld s0, 16(sp)
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; RV64-NEXT: ld ra, 24(sp)
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; RV64-NEXT: addi sp, sp, 32
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; RV64-NEXT: ld ra, -8(s2)
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; RV64-NEXT: addi s2, s2, -8
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; RV64-NEXT: ret
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%res1 = call i32 @bar()
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%res2 = call i32 @bar()
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%res3 = call i32 @bar()
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%res4 = call i32 @bar()
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%res12 = add i32 %res1, %res2
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%res34 = add i32 %res3, %res4
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%res1234 = add i32 %res12, %res34
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ret i32 %res1234
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}
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define i32 @f5() shadowcallstack nounwind {
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; RV32-LABEL: f5:
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; RV32: # %bb.0:
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; RV32-NEXT: sw ra, 0(s2)
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; RV32-NEXT: addi s2, s2, 4
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp)
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; RV32-NEXT: call bar
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; RV32-NEXT: lw ra, 12(sp)
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: lw ra, -4(s2)
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; RV32-NEXT: addi s2, s2, -4
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; RV32-NEXT: ret
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;
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; RV64-LABEL: f5:
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; RV64: # %bb.0:
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; RV64-NEXT: sd ra, 0(s2)
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; RV64-NEXT: addi s2, s2, 8
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp)
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; RV64-NEXT: call bar
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; RV64-NEXT: ld ra, 8(sp)
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ld ra, -8(s2)
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; RV64-NEXT: addi s2, s2, -8
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; RV64-NEXT: ret
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%res = call i32 @bar()
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%res1 = add i32 %res, 1
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ret i32 %res
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}
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