66073953a5
There seems to be a small benefit to the legalized sequence for v2f16 round with packed instructions, so allow vectorizing it by reducing the cost. An unintended side effect is vectorization of f32 round also happens. The current FMA logic seems off to me, and isn't checking for packed instructions.
39 lines
1.5 KiB
LLVM
39 lines
1.5 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s
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; GCN-LABEL: @round_v2f16(
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; GFX7: call half @llvm.round.f16(
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; GFX7: call half @llvm.round.f16(
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; GFX8: call <2 x half> @llvm.round.v2f16(
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define <2 x half> @round_v2f16(<2 x half> %arg) {
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bb:
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%tmp = extractelement <2 x half> %arg, i64 0
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%tmp1 = tail call half @llvm.round.half(half %tmp)
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%tmp2 = insertelement <2 x half> undef, half %tmp1, i64 0
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%tmp3 = extractelement <2 x half> %arg, i64 1
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%tmp4 = tail call half @llvm.round.half(half %tmp3)
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%tmp5 = insertelement <2 x half> %tmp2, half %tmp4, i64 1
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ret <2 x half> %tmp5
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}
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; TODO: Should probably not really be vectorizing this
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; GCN-LABEL: @round_v2f32(
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; GCN: call <2 x float> @llvm.round.v2f32
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define <2 x float> @round_v2f32(<2 x float> %arg) {
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bb:
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%tmp = extractelement <2 x float> %arg, i64 0
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%tmp1 = tail call float @llvm.round.f32(float %tmp)
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%tmp2 = insertelement <2 x float> undef, float %tmp1, i64 0
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%tmp3 = extractelement <2 x float> %arg, i64 1
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%tmp4 = tail call float @llvm.round.f32(float %tmp3)
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%tmp5 = insertelement <2 x float> %tmp2, float %tmp4, i64 1
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ret <2 x float> %tmp5
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}
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declare half @llvm.round.half(half) #0
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declare float @llvm.round.f32(float) #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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