708084ec37
These headers used to be guarded only on PowerPC64 Linux or FreeBSD, but they can also be enabled for AIX OS target since it's big-endian ready. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D129461
58 lines
3.1 KiB
C
58 lines
3.1 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: native, powerpc-registered-target
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// UNSUPPORTED: !powerpc64-
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// The stdlib.h included in mm_malloc.h references native system header
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// like: bits/libc-header-start.h or features.h, cross-compile it may
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// require installing target headers in build env, otherwise expecting
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// failures. So this test will focus on native build only.
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// RUN: %clang -Xclang -no-opaque-pointers -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s
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// RUN: %clang -Xclang -no-opaque-pointers -target powerpc64-ibm-aix -S -emit-llvm %s -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s
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#include <mm_malloc.h>
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void __attribute__((noinline))
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test_mm_malloc() {
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char *buf = _mm_malloc(100, 16);
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_mm_free(buf);
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}
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// CHECK-LABEL: @test_mm_malloc
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// CHECK: define internal i8* @_mm_malloc(i64 noundef [[REG1:[0-9a-zA-Z_%.]+]], i64 noundef [[REG2:[0-9a-zA-Z_%.]+]])
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// CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = alloca i8*, align 8
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// CHECK: store i64 [[REG1]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
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// CHECK-NEXT: store i64 [[REG2]], i64* [[REG5:[0-9a-zA-Z_%.]+]], align 8
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// CHECK-NEXT: store i64 16, i64* [[REG6:[0-9a-zA-Z_%.]+]], align 8
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// CHECK-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
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// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
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// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = icmp ult i64 [[REG8]], [[REG9]]
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// CHECK-NEXT: br i1 [[REG10]], label %[[REG23:[0-9a-zA-Z_%.]+]], label %[[REG24:[0-9a-zA-Z_%.]+]]
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// CHECK: [[REG23]]:
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// CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
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// CHECK-NEXT: store i64 [[REG25]], i64* [[REG5]], align 8
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// CHECK-NEXT: br label %[[REG24:[0-9a-zA-Z_%.]+]]
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// CHECK: [[REG24]]:
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// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
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// CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG4]], align 8
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// CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = call signext i32 @posix_memalign(i8** noundef [[REG29:[0-9a-zA-Z_%.]+]], i64 noundef [[REG26]], i64 noundef [[REG27]])
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// CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = icmp eq i32 [[REG28]], 0
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// CHECK-NEXT: br i1 [[REG30]], label %[[REG31:[0-9a-zA-Z_%.]+]], label %[[REG32:[0-9a-zA-Z_%.]+]]
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// CHECK: [[REG31]]:
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// CHECK-NEXT: [[REG33:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG29]], align 8
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// CHECK-NEXT: store i8* [[REG33]], i8** [[REG3]], align 8
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// CHECK-NEXT: br label %[[REG19:[0-9a-zA-Z_%.]+]]
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// CHECK: [[REG32]]:
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// CHECK-NEXT: store i8* null, i8** [[REG3]], align 8
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// CHECK-NEXT: br label %[[REG19:[0-9a-zA-Z_%.]+]]
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// CHECK: [[REG19]]:
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// CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG3]], align 8
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// CHECK-NEXT: ret i8* [[REG34]]
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// CHECK: define internal void @_mm_free(i8* noundef [[REG35:[0-9a-zA-Z_%.]+]])
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// CHECK: store i8* [[REG35]], i8** [[REG36:[0-9a-zA-Z_%.]+]], align 8
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// CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i8*, i8** [[REG36]], align 8
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// CHECK-NEXT: call void @free(i8* noundef [[REG37]])
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// CHECK-NEXT: ret void
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